Low End FPGAs

So I'm looking at various platforms for general purpose, fairly low-end
FPGAs, and it looks like the Lattice ECP5, Xilinx Artix-7, and Altera
Cyclone V E all have options in the sort of
* 170ish IO
*
Enough logic to do PLDy sort of tasks
* $20ish in ~100p quantity.
I've used Vivado, and Vivado's got its issues. I've used the latest
Quartus Prime, and Quartus Prime's got its issues. Haven't used Diamond
yet, but I'm guessing Diamond's got its issues.
Has anyone been playing with any (or even better multiple) of these and
got any opinions one way or another on which to go with? Or do I just
roll a die?
--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
 
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Reply to
Rob Gaddi
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If you are happy with Lattice you might consider the LFXP2-5E-5FTN256C. 172 I/Os, 5 kLUTs, 18 kB (9 bit bytes) block RAM, 3 DSP blocks and 12 multipliers. It is Flash rather than RAM based (or more accurately both), so no external Flash. The best part is it's $13 at qty 100.
Lattice also has their ice40 line which has RAM and one time programmable NV memory. They have two lines, low power and high performance, LP8K and HX8K respectively. Both parts have 7,680 LUTs, 32 block RAMs (4 kbit) and no math components.
I haven't used these parts, I've used the XP series. The Diamond software uses Synplicity and ActiveHDL for synthesis and simulation and seems to work ok. VHDL 2008 seems to be supported pretty well.
--

Rick C
Reply to
rickman
The smallest Xilinx Spartan 3E is quite affordable, if you need just a little logic. There's also the CoolRunner II and XC9536XL for really small jobs, these are only $1 - $2 each.
Jon
Reply to
Jon Elson
My concern is longevity for new designs. Xilinx's decision to not bring any of the Spartan family forward to Vivado sounds a whole lot like "Well, we're not NOT supporting them, but..."
Altera's decision to drop Quartus support for Cyclone III, even though they still support the Cyclone IV which is nothing but a die shrink, is equally irksome.
--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
 
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Reply to
Rob Gaddi
I've been very happy playing with Max 10. There's a dev board for 30$ which is really cheap but has 8K logic elements, sdram, etc.
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For a medium design (Z80 CPU and peripherals) my compilation times were ~10-15 minutes if I remember correctly with the free edition of Quartus.
I also found the free included SignalTap logic analyzer very useful in debugging the design-- I've heard that Xilinx charges for the logic analyzer part which swayed me in Altera's direction.
The chip itself is also pretty cheap in small quantities (~~10$)
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What applications are you looking to implement and what other factors are important to you?
Reply to
Emilian Miron
Fortunately, Xilinx does archive their older tools. I just had to bring back an ise ver 10.1 system to make a change to a legacy design on Spartan 2E. I'm running ise 14.7 for my current products using 95**XL and Spartan 3A, and happy with them, no desire to update and learn any new software.
Glad to know Xilinx isn't the only outfit doing this.
Jon
Reply to
Jon Elson
No, I don't think that is true. I'm pretty sure ChipScope is included even in the WebPack, although it probably has size limits or something. At least for the versions I'm using.
Jon
Reply to
Jon Elson
This has changed recently, luckily... Unfortunately, the user experience of ChipScope is in no way comparable with SignalTap, at least IMHO.
Thomas
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Reply to
thomas.entner99
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Also Altera allows you to download their old software. In both cases this m ay help you out in short term, but in long term you may have issues install ing this versions on a modern system. (e.g. if you want to maintain a FLEX1 0K design - not sure if MAX+PLUS II installs on Win 10 64b...) (of course i t is more Microsoft to blame here...)
From my outside view the difference is, that Vivado does not support old de vices as it is "too much of a challange" for Xilinx, while Quartus stops su pporting older devices because of political decisions form Altera (which ar e not clear to me? Urging people into new devices? In reality it is more fo rcing customers to stay at older versions... For some parts it may make sen se from a maintenance point of view, but as someone already mentioned e.g. Cyclone III and IV are internally the same).
Both is equally frustrating....
Thomas
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Reply to
thomas.entner99
Altera: I would also consider the MAX10 family Xilinx: The have announced Spartan-7 some time ago, but beside this (remarkingly low content) announcement, I do not know about the status of this. So it seems you have to look at Artix-7 as you already do Lattice: MachXO2/3 should be you part
My very personal opinion on software rating: 1. Quartus (esp. small designs benefit from the "more responsive" feeling of the GUI - I am talking about 15.0 here, have not used Prime yet) 2. Vivado (Although I like the integrated simulator a lot) 3. Diamond (however, have not used it since a while)
But for sure you can get your work done with all of them, so this discussion is highly subjective.
Thomas
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Reply to
thomas.entner99
Unless you have very good relationships with your local Altera reps, getting what you want with Cyclone V E sounds almost impossible. On the other hand, Cyclone IV E (e.g. EP4CE6) should be easily in your range.
Even if your logic requirement are higher than EP4CE6, EP4CE15 still can be cheaper option than 5CEA2.
Reply to
already5chosen
If they can't be compared, how would anyone know which is better?...
--

Rick C
Reply to
rickman
It is simple economics. Verification is the expensive part of software. Removing the verification effort for older devices is a big time and money savings with little cost in terms of sales.
I learned a long time ago that FPGA companies focus on whatever is the latest generation not caring one whit about sales of older generations. The return for efforts promoting the older generations will always be a lot less than for promoting the latest generation. So the lack of full support at some point is inevitable.
--

Rick C
Reply to
rickman
Am Freitag, 26. August 2016 02:04:34 UTC+2 schrieb Rob Gaddi:
You might also consider Microsemi (former known as Actel) Igloo FPGAs.
Those have their configuration flash on die and are live at power-up without image loading time, which is typically good for PLD like applications.
regards,
Thomas
Reply to
Thomas Stanka
My few experiences with ChipScope have not been great, but it does work to figure out what is going wrong. Best to do the best simulations you can do first, then maybe try to come up with likely scenarios for the failure and check your FPGA code would handle them properly. If you can't solve it that way, then go to ChipScope and maybe you can trap the condition. No need to ever use it for entirely within the FPGA logic, only when interaction with something outside is going astray.
Jon
Reply to
Jon Elson

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