Field-Programmable Gate Arrays

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verilog code

hi, i want verilog code for RS232
5 comments posted 9yrs
posted by koradaprudvi
5 comments posted 9yrs posted by koradaprudvi

Go to church today

Go to church today. Get yourself back on the right track again. Say a little prayer asking God to help you. He will. Bes...
0 comments posted 9yrs
posted by rick.c.hodgin
0 comments posted 9yrs posted by rick.c.hodgin

entity component binding issue with configurations

I have binding warnings http://paste2.org/La9jIxbF with http://paste2.org/wnHDY0g3 How do I solve them ? even I modify...
3 comments posted 9yrs
posted by user123random
3 comments posted 9yrs posted by user123random

How much is your life worth?

How much is your life worth? There are a lot of hypocrites in this world ... Christians who call themselves by that nam...
0 comments posted 9yrs
posted by rick.c.hodgin
0 comments posted 9yrs posted by rick.c.hodgin

CORDIC in a land of built-in multipliers

Now that FPGAs have built-in DSP blocks, how commonly is CORDIC used? Is it still a necessary go-to for anyone contempl...
28 comments posted 9yrs
posted by seemywebsite
28 comments posted 9yrs posted by seemywebsite

Eternal life

Did you know you are an eternal being? And that you will go on after you leave this world? What's on the other side? Wh...
0 comments posted 9yrs
posted by rick.c.hodgin
0 comments posted 9yrs posted by rick.c.hodgin

19 minutes to Life

A 30-something female describes the deception of the enemy in thinking Heaven is attainable by works or morals. It isn'...
11 comments posted 9yrs
posted by rick.c.hodgin
11 comments posted 9yrs posted by rick.c.hodgin

Help with multiplier code

Hi, I am having problem with https://ptpb.pw/4Twc , https://ptpb.pw/UpJX and http://i.imgur.com/wGEVxuL.png It just cou...
0 comments posted 9yrs
posted by user123random
0 comments posted 9yrs posted by user123random

Vivado HLS (C/C++/SystemC to ASIC/FPGA)

Does anybody have experience with Vivado HLS? https://www.xilinx.com/products/design-tools/vivado/integration/esl-desig...
1 comments posted 9yrs
posted by rick.c.hodgin
1 comments posted 9yrs posted by rick.c.hodgin

xilinx aurora lane order

Guys I have two FPGAs with 4 MGTs connected between them using Aurora. The firmware guy has insisted (and I've taken a...
3 comments posted 9yrs
posted by colin_toogood
3 comments posted 9yrs posted by colin_toogood

How do I preserve Hazard safety terms?

for muxen. during combinatorial optimization. in berkeley-abc. I am using the binary aig format for importing. It knows...
8 comments posted 9yrs
posted by klammerj
8 comments posted 9yrs posted by klammerj

C to FPGA

An interesting video: C to FPGA Compilation and Domain-Specific Computing https://www.youtube.com/watch? v=TNF8EhKDM1c...
6 comments posted 9yrs
posted by rick.c.hodgin
6 comments posted 9yrs posted by rick.c.hodgin

Sharing a single Lookup Table

I am implementing the gamma correction LUT as in https://ptpb.pw/ZwYS if I want to share a single combinatorial lookup...
1 comments posted 9yrs
posted by user123random
1 comments posted 9yrs posted by user123random