# Constant Mult: The State of High Level Synth (Part II)

• posted
Here's another example that shows just how far removed we are from high-level synthesis.
I need to multiply a 10-bit number by 956. I could use a DSP48, but it's overkill, and to meet timing I'd probably have to pipeline it fully and have 3 cycles of latency. So I write this code and force Vivado not to use DSP48s:
reg [9:0] x; // multiplicand
reg [19:0] p; // product
always@(posedge clk)
p
• posted
I realized that in my application, x probably only needs to be 6 bits wide. So I synthesized that, and got something with carry chains in it. Wait a minute... if each LUT is a 64-bit lookup table, wouldn't you synthesize a constant multiplication by a 6-bit multiplicand as a lookup, with 1 LUT per output bit and 1 level of logic? Yes, you would. No carry chains. But i n order to do that, I had to write the logic like this:
reg [5:0] x; always@(posedge clk) case(x) 0: p
• posted
Interestingly, the following loop also implements the multiply as a lookup table with 1 LUT per output bit without having to write out the case statem ent.
reg [5:0] x; integer ii; always@(posedge i_clk) for (ii=0; ii
• posted
looks like they don't do optimization on that stuff... have you tried yosys? I'm pretty sure It'll do that for you. or perhaps bare ABC... if you have some other way to convert to blif or AIG or sthg...
or perhaps you've missed some synth option...?
• posted
I imagine Synplify would do a better job, but I don't have it. It seems li ke Vivado just wants to do any multiplication in a DSP48, and if you don't do that, it has poor heuristics. If I were going to need this a lot, I'd j ust make my own function with some good heuristics (e.g., if it's a constan t mult and the constant has a CSD representation with
• posted
Speaking as someone who does mostly software and circuit design, with enough FPGA knowledge to be dangerous -- the optimizer doesn't seem to be trying very hard.
```--
Tim Wescott
Control systems, embedded software and circuit design ```
• posted
Could it be that when you tell the thing to not use a DSP block it's interpreting that to mean "just don't optimize this"?
```--
Tim Wescott
Control systems, embedded software and circuit design ```

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