Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15253 Threads Posts
to

Graduate/Junior FPGA Designer concerns

I have and odd question. As a final year student at EE course (thesis is a complex FPGA project) I am starting to get c...
7 comments posted 19yrs
posted by freeplatypus
7 comments posted 19yrs posted by freeplatypus

Help configuring XUP PPC for Ethernet

Hi everyone, We are a group of Computer Science students working on a project on the XUP board's PowerPC processor core...
1 comments posted 19yrs
posted by islam.ossama
1 comments posted 19yrs posted by islam.ossama

fitting problem on A54SX72A

Hi everyone, I have a strange behaviour in my implementation even if the design is pretty simple (even if it's very den...
6 comments posted 19yrs
posted by alessandro.basili
6 comments posted 19yrs posted by alessandro.basili

anyone know a FPGA designer?

hi, I need to design and implement a very simple FPGA. There will be 34 TTL inputs. One (and only one) will be tripped...
6 comments posted 19yrs
posted by jonyt
6 comments posted 19yrs posted by jonyt

How to measure clock fequency

Dear I am confused to obtain real "clock frequency" of my 2 implementations. Implementation details are following. In U...
0 comments posted 19yrs
posted by pasacco
0 comments posted 19yrs posted by pasacco

EDK - Microblaze question

Is there a method of using external RAM (Generic external Memory) where the data, heap and stack can be located? Ideall...
5 comments posted 19yrs
posted by fred
5 comments posted 19yrs posted by fred

Simulating analogue signal using ISE simulator

Hello all, Whenever I need to look at a filter output (or any DSP core), I used to define a real signal and assign it to...
2 comments posted 19yrs
posted by mloulah
2 comments posted 19yrs posted by mloulah

ispLever 7.0

Evnin' Just received the download link for ispLever 7.0 and read the announcement... Is it really true that 7.0 support...
0 comments posted 19yrs
posted by me
0 comments posted 19yrs posted by me

V4FX60, hard temac, MPMC2 and SoDIMM

Has anyone instantiated a MPMC2 interfaced to a SoDIMM and the following ports: 1) ISPLB (for the ppc405) 2) ISPLB (for...
1 comments posted 19yrs
posted by morphiend
1 comments posted 19yrs posted by morphiend

what is the correct way to capture ADC using fpga

Hi, can anyone tell me what is the correct way to capture data from 60 mh sampling, 16 bits ADC? Should I use 4 differe...
8 comments posted 19yrs
posted by ckh827
8 comments posted 19yrs posted by ckh827

Xilinx FPGA Pinout spreadsheets

Hi, I have a vague memory that Xilinx used to provide excel spreadsheets that showed the graphical pinout of each FPGA...
5 comments posted 19yrs
posted by rob.dimond
5 comments posted 19yrs posted by rob.dimond

Help on clock forwarding with Virtex-5

Hi, (Sorry that if I sent this more than once. Somehow, my email client just doesn't function well.) I'm new to FPGA wo...
0 comments posted 19yrs
posted by chinchia.kuo
0 comments posted 19yrs posted by chinchia.kuo

Need help on clock forwarding on Xilinx Virtex-5

Hi, I'm new to FPGA world and currently working on an emulation board with 2 Virtex-5. I think to forward clock from ch...
0 comments posted 19yrs
posted by ggkuo
0 comments posted 19yrs posted by ggkuo

help on clock fowarding between 2 FPGAs

Hi, I'm new to FPGA world and currently working on an emulation board with 2 Virtex-5. I think to forward clock from ch...
5 comments posted 19yrs
posted by ggkuo
5 comments posted 19yrs posted by ggkuo