Dear
I am confused to obtain real "clock frequency" of my 2 implementations.
Implementation details are following.
In UCF file, (1) "CLK" is connected to Virtex-II Pro clock pin. (2) I constrained the clock "CLK" as 10 ns.
Inside the design module, DCM is instantiated. DCM generates a signal with two times frequency, "CLK2X".
Finally, following report was obtained.
------------------------------------------------------------ Implementation 1
----------------------------------------------------------- Constraint 1 = TS_Inst_DCM1_CLK2X_BUF = PERIOD TIMEGRP "Inst_DCM1_CLK2X_BUF" TS_CLK / 2 HIGH 50%
Requested = 5.000ns Actual =3.683ns
--------------------- Constraint 2 = TS_Inst_DCM1_CLK0_BUF = PERIOD TIMEGRP "Inst_DCM1_CLK0_BUF" TS_CLK HIGH 50%
Requested = 10.000ns Actual = 4.565ns
------------------------------------------------------------
------------------------------------------------------------ Implementation 2
----------------------------------------------------------- Constraint 1 = TS_Inst_DCM1_CLK2X_BUF = PERIOD TIMEGRP "Inst_DCM1_CLK2X_BUF" TS_CLK / 2 HIGH 50%
Requested = 5.000ns Actual =4.897ns
--------------------- Constraint 2 = TS_Inst_DCM1_CLK0_BUF = PERIOD TIMEGRP "Inst_DCM1_CLK0_BUF" TS_CLK HIGH 50%
Requested = 10.000ns Actual = 2.929ns
------------------------------------------------------------
Question is that
Is following statement correct?
Clock period of Implementation 1 = 4.565ns Clock period of Implementation 2 = 4.897ns
Thank you in advance for any comment.