Hi everyone, I have a strange behaviour in my implementation even if the design is pretty simple (even if it's very dense!). I have a decoding block which gets "address" to write data into several registers. The decoding block is such that it will produce an enable signal for each single register. Then a "write" signal is distributed with some latency such that propagation delays are taken into account. What I find is that for postsynthesis simulation everything is fine, but in my postlayout I have some addresses which are enabled even if the address is another one, turning out that I write two registers at once. I can't really understand why!
Here is a sketch of my vhdl code:
So it happens that writing to addr = x"123" it will change signal2 as well...how can it be possible???
I did prefer to have "p_signals" and not use directly the "addr" in the process just because in the very beginning I thought about latching the "p_signals" to have them stable, but then I realized it wouldn't have fit in the logic (I have already an occupancy of 84% and I have more than 300 addresses to decode). Do you have any explanation of this behaviour?
Thanks a lot for any comment
Al