Latest threads in Field-Programmable Gate Arrays

How to make a small (<4Kbyte) program for V4 PPC

I am trying to make a 4 Kbyte program to go in isocm at the top of PPC address space. It seems to build OK. But when I...

4 19yrs

jcc

4 19yrs jcc

booting a large V4 PPC program with a minimum of on chip bram

I am trying to boot the PPC with a minimum of block ram, since I want to save that for my own hardware peripherals. My...

4 19yrs

jcc

4 19yrs jcc

edk clock problem

Dear all, I am a graduate student at USF. I am working with XILINX XUPV2P board and i am using edk to interface memory...

0 19yrs

mahalingamv

0 19yrs mahalingamv

What is LatticeSC implementation of Virtex-4 ISERDES and OSERDES

Hi, For those who are familiar with Lattice/LatticeSC, what is LatticeSC implementation of Virtex-4 ISERDES and OSERDES...

0 19yrs

yy7d6

0 19yrs yy7d6

Quartus Timing Analyzer question

Hi. I am working with Alera Quartus software on FPGA realization of STFT(Short Time Fourier Transform) and I have one p...

5 19yrs

Zorjak

5 19yrs Zorjak

Using LogicLock in Altera Quartus II

Hello, I'm looking for opinions on using LogicLock in Quartus II, is it useful or a waste of time? What are some of your...

2 19yrs

jjlindula

2 19yrs jjlindula

problems with FSL and Microblaze

I=B4m developing a FSL Peripheral. I=B4m having the following problem: when trying to generate the bitstream it generat...

4 19yrs

dmendesf

4 19yrs dmendesf

c code to initialize a peripheral

Hi everybody I am trying to familiar to xps software .So i am trying to create a peripheral using 2kb bram block in whi...

5 19yrs

rajivc53

5 19yrs rajivc53

LogicSim v3.0 Verilog Simulator is Here!

LogicSim v3.0, an affordable and user-friendly Verilog simulator for ASIC and FPGA design verification is finally here....

0 19yrs

ngsayjoe

0 19yrs ngsayjoe

ISE write permissions?

9.1 SP3 on XP. I can open my project from the "File" dialog, but if I try double-clicking the ISE file I get: "The proj...

3 19yrs

pfraser

3 19yrs pfraser

custom peripheral registers

Hi everybody, i' trying to realize a custom OPB peripheral using EDK. In my design I need a register in which one bit s...

5 19yrs

cispa

5 19yrs cispa

Incremental Compilation in Altera Quartus II version 7.1

Hello, I was wondering if anyone is using Incremental Compilation in Quartus 7.1 and if so, could you comment on it. Is...

2 19yrs

jjlindula

2 19yrs jjlindula

Recommendation for creating a DDR Sdram core for custom board and integrate in XPS

This is not the first time I ask for this problem, but at the moment I go on trying to solve this problem. I have a cus...

7 19yrs

pbantunez

7 19yrs pbantunez

ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s

ON NEXT MONDAY : 17-JUNE-2006 Amontec will provide the ?how-to? program via a XILINX VIRTEX XC4VLX25 7.9Mbits bit strea...

29 19yrs

laurent.gauch

29 19yrs laurent.gauch

how to speed up the write to the off chip ram

Hi, I have a core which generates 400+ parallel outputs per once. Each output can take only 3 possible values only: A,B...

0 19yrs

tlenomade

0 19yrs tlenomade