what is the correct way to capture ADC using fpga

Typically the design engineer evaluates the clock-to-out of the ADC and the input setup/hold times of the FPGA input registers in the IOB. If the FPGA uses a DCM, the phase of the DCM can be adjusted or the delay to the input registers can be adjusted. It may be that a DCM isn't required at all. If the timing values cannot be evaluated beforehand, it may be that a synamic approach is required but that's doubtful.

How you store the data depends on what you want to do with it. Streaming applications require no storage, just work-in-process. Data acquisition systems need larger external memories that often use BlockRAMs as intermediate storage to buffer DMAs or burst transfers.

Whatever you do, please don't use the DCM to generate the clock for the ADC since it could raise the noise floor of the ADC output significantly. Instead, use the clean clock that feeds the ADC to run the FPGA.

- John_H

mhz

If

synchronize

the

FPGA

input

If

synamic

ADC

Hi John. I have to interface two ADC to my fpga. Should I use one mai clock for everything? Since there are not in the same PCB, is that ok t use wires to connect all three boards' clock? Would that generat unnecessary problem like noise?

thank you for replying me John,

Are you feeling like you're in over your head on this project?

Do either/both of your ADC boards have clock input or output available? Does your FPGA board have a clock input or a buffered clock output from the main oscillator? Do you need synchronized operation of your ADC boards or can they run at two different frequencies?

How are you bringing the ADC data across to the FPGA board? Are you using wires?

_____

I'm sorry that I can't provide you with my DCM phase shift code for your other matter.

I am curious as to know the reason behind not using fpga generated clock to drive the adc. Is it because they have higher amount of jitter? I am in the process of designing a datapath from adc to the fpga.

Thanks.

-sanjay

The jitter is the problem. For a high speed ADC, the error from jitter can approach the ratio of the jitter to the clock period for a properly band-limited input signal. For a direct IF sampling system, the error can exceed that ratio. If you think of the voltage slewing on the ADC input, the error in the sample point corresponds directly in a voltage error; if the sample was ideally zero volts, the jitter makes the actual sample further up or down that rapidly changing voltage.

The noise floor will be noticeably raised in a fast system. The cleanest way to work with an FPGA/ADC system is to use the clean clock to drive the ADC and the FPGA, no daisy chaining. If you *must* use an FPGA to drive the clock (if you're doing phase modulation of the sampling, for instance) then a cleanup PLL is required to get the noise down to an acceptable level.

FPGAs are superb for logic. They are not designed to function as analog elements. The DCMs are well specified and perform very well for even the most demanding logic. But DCMs are not analog quality. Treat them as analog noise sources! The jitter is the biggest issue.

- John_H

Thanks John for this insight. Very helpful. But this has raised some questions in my mind. Xilinx uses DCMs and they add jitter to the clocks. On the other hand Altera uses PLLs and they actually filter out the jitter. So in this case it would be good to go with an Altera device and drive the clocks to ADC? Or do you see some other problems as well.

Thanks.

-sanjay

The use of a PLL will help your situation. But keep in mind that FPGAs are ALL concerned with digital signals and are NOT designed as analog devices! Although the Altera device has significantly less jitter than the Xilinx DCM output, the output will be contaminated by other FPGA characteristics. Just having other I/O switching on the same bank is enough to generate noise in the output clock.

Your best bet is to NEVER drive the ADC directly from your FPGA independent of the brand.

But you can get by without the cleanup PLL (the dedicated, external analog device) *if* you do an error analysis to determine how much jitter is tolerable on your ADC clock. If, for instance, you have an audio stream used for communications (14 bits or fewer at 8 kS/s, encoded to 8 bits) then your worries are pretty limited. If you have a

16-bit ADC running at 400 MHz, you're in a world of hurt without extreme design constraints for a clean sampling timebase.

You will ALWAYS benefit from having a fixed sampling clock fed to the ADC from the oscillator rather than from the FPGA. If that clock topology is impractical, you have to decide how much error or noise floor is acceptable for your application and guarantee that your logic device won't degrade the clock beyond your acceptable level. While the Altera solution *may* be better than the Xilinx solution by 20 dB, I would suspect the improvement is more on the order of 12-14 dB without extreme care in the power supply and I/O activity for the Altera alternative. I don't have evidence to support my numbers, just expectations in raw performance.

- John_H

Thanks John. This is great stuff. I also found a recent article that confirms your thesis. 5 stars to your post.

-sanjay