Field-Programmable Gate Arrays

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synthesis translate_off

Does anyone if "//synthesis translate_off" in Xilinx is also honored by ASIC synthesis tool (Design compiler) ? Thanks
1 comments posted 19yrs
posted by chinchia.kuo
1 comments posted 19yrs posted by chinchia.kuo

SystemC - Libero IDE

Hi all, just for curiousity anyone knows if Actel is working on some tools to include SystemC synthesis in the future f...
2 comments posted 19yrs
posted by claesvincent
2 comments posted 19yrs posted by claesvincent

Rocketio connection Virtex2pro-Virtex4

Hi everyone, Could someone with experience or simulation tools provide information on the hardware requirements to inte...
3 comments posted 19yrs
posted by nospam
3 comments posted 19yrs posted by nospam

How do i add my IP to EDK?

Hi, I have designed a IP core, how can i add my IP to EDK? Anyone who can help me?
2 comments posted 19yrs
posted by rbmm756
2 comments posted 19yrs posted by rbmm756

spartan 3A : DDR2 controller

for edu. purpose, I would like to modify s3astarter_ddr2 design to use it with picoblaze (store some data to ddr2 and r...
1 comments posted 19yrs
posted by rponsard
1 comments posted 19yrs posted by rponsard

XPower: Can't change activity rates

Hi, I have created a .vcd file using modelsim and am trying to estimate the power consumption for my design. The proble...
0 comments posted 19yrs
posted by smerchan
0 comments posted 19yrs posted by smerchan

V5 GTP Sim Problem

I am trying to simulate the V5 GTP in ModelSim SE and am having trouble. I have compiled the sim libraries, followed th...
2 comments posted 19yrs
posted by mottoblatto
2 comments posted 19yrs posted by mottoblatto

.xco file and vcs verilog compiler

I have a Xilinx design that uses mainly verilog RTL and some .xco file for coregen FIFOs and such. I am using vcs compi...
2 comments posted 19yrs
posted by
2 comments posted 19yrs posted by

No serial output while booting a Xilinx ML403 board

Hello, I am new to the embedded world and I am having a problem getting a Xilinx ML403 board to output any info while i...
2 comments posted 19yrs
posted by gseegmiller
2 comments posted 19yrs posted by gseegmiller

Tecis-Termin

Hast mich ganz sch=F6n geweckt heute morgen... wenn Du so lange snoozed und nicht raus kommst werd' ich wach. Ich hab'...
0 comments posted 19yrs
posted by phq
0 comments posted 19yrs posted by phq

how to assert PSEN for DCM

Hi all In the datasheet, psen has to be asserted before rising edge of psclk fo one clock. How can I implement this? Sh...
1 comments posted 19yrs
posted by ckh827
1 comments posted 19yrs posted by ckh827