how to assert PSEN for DCM

Hi all In the datasheet, psen has to be asserted before rising edge of psclk fo one clock. How can I implement this? Should I use the clock to driv psclk as the clock of my state machine? If so, then

------------------------------------------- always @ (posedge PSCLK_clk) begin // other logics.... PSEN

Reply to
cutemonster
Loading thread data ...

PSEN will go high a little bit AFTER the rising edge of the clock. The next rising edge of the clock presumably sets the signal to 0. It will actually be 0 a little time AFTER the rising edge of the clock. The time between those two events is one clock cycle.

Reply to
motty

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.