PSEN will go high a little bit AFTER the rising edge of the clock. The next rising edge of the clock presumably sets the signal to 0. It will actually be 0 a little time AFTER the rising edge of the clock. The time between those two events is one clock cycle.
Read the full replyHi all In the datasheet, psen has to be asserted before rising edge of psclk fo one clock. How can I implement this? Should I use the clock to driv psclk as the clock of my state machine? If so, then
------------------------------------------- always @ (posedge PSCLK_clk) begin // other logics.... PSEN
PSEN will go high a little bit AFTER the rising edge of the clock. The next rising edge of the clock presumably sets the signal to 0. It will actually be 0 a little time AFTER the rising edge of the clock. The time between those two events is one clock cycle.
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