I have a Xilinx design that uses mainly verilog RTL and some .xco file for coregen FIFOs and such. I am using vcs compiler from synopsys. This compiler does not recgonize the xco files. Is there any way I can convert .xco file into verilog file using Xilinx coregen?
I do not know why this shareware design does not provide the verilog file for coregen fifo and instead it has the .xco file. Is there any advantage in doing so?
It will be great if I can convert the .xco file into .v for vcs verilog simulation. vcs compiler is able to compile the xilinx primitves .v files provided by Xilinx.
Thanks for your help.
Maverick