Help needed regarding addition of Custom IP core to EDK

Is your pao file implemented correctly? That's the first thing that popped into my head.

So is the simpl_tx (that is how you spelled it above - maybe that's the problem?) a verilog file? As far as I know, the pao needs to specify that in the analyze order. There's no reason that you can't have a FIFO core ngc and HDL files in the same IP.

Hi ,

Yes I have included this in the periperal analyze order (Pao ) .

The problem is When I try to add a coregen IP ( I generated the IP with Verilog becoz I was more comfortable with that) to my EDK , I followed all the necessary steps.

EDK defaultly thinks that I have the generated the IP using Coregen using VHDL option and goes to the directory :

Fifo_test_v1_00_a/hdl/vhdl/simpl_tx.vhd

But It shoud actually go to the directory

Fifo_test_v1_00_a/hdl/verilog/simpl_tx.v

I d> Is your pao file implemented correctly? That's the first thing that

The EDK will search the libraries you list in the pao. I do all my cores in verilog and don't ever have problems.

I don't understand what you mean by the EDK going 'defautly' to the vhdl folder. Is simpl_tx the fifo? If it is, put the verilog file (generated by core gen) in the hdl/verilog folder and include it in the pao. Then put the ngc in the netlist folder and include it in the bbd file.

Somehwere/somehow the EDK thinks it is searching for a VHDL file called simpl_tx...and I really don't think that is in a script anywhere....at least one that isn't generated via files you have access to in the core.

Post the pao (at least to make me shut up about that). I can't think of why your core is behaving badly. But maybe if it was in front of me I'd understand better.