Latest threads in Field-Programmable Gate Arrays

Help with Libero IDE and Verilog...

Hi all, I recently purchased the Actel Fusion Starter Kit. I'm new to both Libero IDE and Verilog and was hoping for so...

2 19yrs

weg22

2 19yrs weg22

CML output swing for V5

I am using V5 GTP. As per my understanding, the GTP output should swing between 1.2V and 700mV and common mode voltage...

13 19yrs

Convert Schematic Files (.sch) to Verilog Files (.v) for simulation in ModelSim

Is there a way to convert a schematic file (.sch) into a functional verilog module (.v/.vf) from the command line? I wa...

11 19yrs

craigtmoore

11 19yrs craigtmoore

Xilinx PCIe endpoint core minimalistic design

Hello, I am implementing a PCIe design for the HiTechGlobal HTG-V4-PCIe60 (Virtex 4 FX60 and FX100) board and having a...

2 19yrs

spacegato

2 19yrs spacegato

Re: Designing the right clock tree for a multi-FPGA setup

Hi - Can you tell us a bit more about your requirements? In particular: - What clock frequency are you distributing? -...

10 19yrs

bobsrefusebin

10 19yrs bobsrefusebin

ASM within C code in a PPC405 of VIRTEX II Pro

Hello, I would like to know how to put ASM instructions in a C code. With a G5 you can do that kind of functions: asm l...

7 19yrs

lpaulo07

7 19yrs lpaulo07

Flex 10k100 & EPC2 redux - forgot the special ingredient?

I posted last year about a strange problem I was having with a Flex 10K100 board. At one time, I figured out how to set...

1 19yrs

jshamlet

1 19yrs jshamlet

Chipscope 9.1: Any easy way to rename and regroup signals?

Hi Xilinx Killers, It is really annoying to rename and group all the signals everytime when design is modified and new...

14 19yrs

yao.sics

14 19yrs yao.sics

New board JTAG error

Hello every one, We have designed a board which contains an ALTERA fpga and an EPROM(EPC2LC20).The design is done with...

2 19yrs

mailsatishv

2 19yrs mailsatishv

Altera MAX III Status ?

Does anyone know the status of the promised Altera MAX III CPLDs ? These were supposed to roll out early in 2007, but t...

5 19yrs

no.spam

5 19yrs no.spam

MiG : Memory Interface (DDR SDRAM) as an ISE schematic symbol

Hi, I am trying to use a Memory Interface generated by MiG (Memory Interface Generator 1.72) as a symbol in a schematic...

10 19yrs

Strange warning message from ise8.2i ?

I have received the following error warning: Cpld:828 - Signal 'done.RSTF' has been minimized to 'GND'. Waiting with ant...

5 19yrs

<miche>

5 19yrs <miche>

Type Conversion in VHDL

hi all, how to convert integer numbers to real numbers and vice-vers. and what will be the hardware generated for real m...

2 19yrs

rakeshujjawal

2 19yrs rakeshujjawal

Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?

Well it's not new at all, but I've just discovered Yet Another Open Source RISC core -- Lattice's Mico32. It comes with...

43 19yrs

anonymous

43 19yrs anonymous

SystemC in modeling HW/SW

Hi, I was told by a friend that SystemC is currently the best to modeling hw/sw design. I've read on the internet where...

2 19yrs

yasirmm

2 19yrs yasirmm

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