Latest threads in Field-Programmable Gate Arraysshow only best voted threads
| Subject | Author | Posted | Replies | |
|---|---|---|---|---|
|
|
lpm_constant function in Altera Quartus 7.1
Hi. Is it buggy again, while using 32-bit hexdecimal number where most significant bit is one? What is the simplest workaround of this?
1
|
16 years ago
|
1 | |
|
|
EDK and ecncrpted .bit, .nky, .mcs files
I'm using EDK to try and produce a produce an encrypted bit file and using Impact an encrypted mcs file. I've looked at the literature but can't find anything about how to do this within EDK. Can...
1
|
16 years ago
|
1 | |
|
|
ISE 9.1i - Process Map Fail without any Error messages
I am using ISE 9.1i. I am getting an error in the Map process which says " Process MAP Fail" without showing any errors. There happens to be bug which was solved in 8.2i Service Pack 1, but still I am...
3
|
16 years ago
|
3 | |
|
|
Virtex-II Pro Flip-Flop Setup time
Hi, For our VHDL design, we are using an evaluation board that has a Xilinx Virtex-II Pro chip on it. The design calls for sampling of a digital signal at 100MHZ. The problem is that the signal...
4
|
16 years ago
|
4 | |
|
|
slave serial configuration of Vertex FPGA using a microcontroller
hi I want to configure a vertex FPGA using a PIC microcontroller in the slave serial mode . I am simply doing the following steps while configuring. 1.Hold prog_b pin low for some time to clear the...
2
|
16 years ago
|
2 | |
|
|
configuring vertex4 FPGA
hi i want to configure a XC4 series of vertex 4 FPGA using a micro controller. which bitgen file is to be ussed for default configuration. Is a title declaration generation for the verterx bitgen...
1
|
16 years ago
|
1 | |
|
|
DDR SDRAM simulation model, ML300, Infineon
Hello all, I m working on an application using DDR SDRAM and i want to simulate (timing simulation) the DDR SDRAM working along with the module i have created. the DDR SDRAM which is implemented on my...
6
|
16 years ago
|
6 | |
|
|
Synplify Problem
I am using Synplicity Synplify Premiere 8.8 and I ran into the problem that it keeps retiming my designs such that a great deal of the logic is placed before the input registers and/or after the...
7
|
16 years ago
|
7 | |
|
|
A Way for a DSP to tell an FPGA to load itself from Flash
Hi, my setup is as follows: 1) DSP ADSP-21065L 2) Xilinx xc3s250 3) Intel JS2BF320J3D Flash I am able to have the DSP load itself from flash but after it's done loading, I would like the DSP to tell...
5
|
16 years ago
|
5 | |
|
|
Problem usign xilfatfs...
I'm trying to get some files of the CF in a XUP board with a VirtexII-pro FPGA, the problem is that I use 'opb_sysace' with xilfatfs library. When I compile the libraries I get the next error: Running...
3
|
16 years ago
|
3 | |
|
|
Error message in ModelSIM PE
Does anyone know what the following error in ModelSIM means? # Loading work.dsss_modem_cosim(structural) # Loading # ** Error: bad arg: "48522 # Executing ONERROR command at macro ./ line 128 Below...
2
|
16 years ago
|
2 | |
|
|
regarding post place and route timing simulation steps........
hi all, i wanted to do the post place and route timing simulation in modelsim. i have got the files form the xilinx ise and i copied both * and *_timesim.vho file into the RTL folder for my...
3
|
16 years ago
|
3 | |
|
|
Spartan3A : timing Constraints / DCM Outputs
Hi Folks, have the following problem and couldn't found out yet how to solve it: I have a clock input CLK_A and a DCM. I use CLKO and CLKFX outputs of DCM. CLKFX is configured for 4X CLK_A. I define...
3
|
16 years ago
|
3 | |
|
|
The delay time of coregen Multiplier in Modelsim
I am using the coregen multiplier. I pre-set the parameters to make the o output latency is 0. Why I simulate it in Modelsim, the output delay time is quite long. Thanks.
—
|
16 years ago
|
— | |
|
|
Adding a bram block to a user defined bram controller
Hi all, We have made a bram controller connected to opb bus now we have to connect a bram block to this controller but there is no port to do tell us how can we achieve this?
—
|
16 years ago
|
— |