Virtex-II Pro Flip-Flop Setup time

Hi,

For our VHDL design, we are using an evaluation board that has a Xilinx Virtex-II Pro chip on it. The design calls for sampling of a digital signal at 100MHZ. The problem is that the signal contains very short pulses, given at random intervals. It's therefore necessary to make sure that the sampler (which is implemented by the flip-flop found in the CLB) can register these pulses, or at least to have an idea of which ones it can register.

So the question is, what is the setup and hold time constraints of those flip-flops? I looked in the datasheet, but couldn't find these figures. The clock to ouput times and so forth were listed, but not this specific setup time. The timing analyzer also didn't give me a satisfying result.

Thanks a lot for your reply, Berk Birand

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Reply to
Berk Birand
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Are you guaranteed a constant phase relationship between you sampler and samplee signals? If not, then it doesn't directly matter what the setup time is (I think I remember Peter saying that they have zero hold time), because the sampled signal is completely asyncronous to the sampling clock and will eventually violate the setup time of the flop, even if its pulses were a day long.

---Matthew Hicks

Reply to
Matthew Hicks

Can you be more exact on what 'very short pulses' actually means ?

If "very short' means 2ns, then you have bigger problems than Tsu. Th :)

You can design pulse capture latches, that will signal the presence of a shorter pulse than your sample rate, but you just know 'it happened in this window', not how narrow it actually was.

The actual FF-Sample-aperture in a modern FF, is well under 1ns, but the actual alignment of that varies with process, routing etc

-jg

Reply to
Jim Granville

Thank your Jim and Matthew for your answers. After a lot of thinking with our project group, we came to the conclusion that setup time wasn't going to be an issue. Since the pulses we have are supposed to be random, we cannot guarantee that they will be synchronized with the clock. So it may violate the setup time, but it turns out that's what we want, since that adds another level of randomness to the problem.

By the way the pulses that we are dealing with are indeed shorter than

2ns. Theoretically, they have a mean width of 1ns. Why did you say we would have bigger problems than Tsetup?

Thanks again for your answers, Berk

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Reply to
Berk Birand

Because you could miss one entirely :)

It sounds however, that you are making effectively a sampling oscilloscope, which relies on the signals being repetitive, and not locked ?

In that context your width-limit will probably be the pin-buffers low-pass effect, but the edge limit will be better - most likely the system jitter. Actual FF aperture times I'd expect to be less than clock jitter time, which is itself less than the system jitter.

You could also use multiple FFs and do some correlation, to see what adjacent channel differences are,

There was another recent thread about mixing clock domains in CPLDs, and the jitter effects of that.

-jg

Reply to
Jim Granville

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