Hi,
For our VHDL design, we are using an evaluation board that has a Xilinx Virtex-II Pro chip on it. The design calls for sampling of a digital signal at 100MHZ. The problem is that the signal contains very short pulses, given at random intervals. It's therefore necessary to make sure that the sampler (which is implemented by the flip-flop found in the CLB) can register these pulses, or at least to have an idea of which ones it can register.
So the question is, what is the setup and hold time constraints of those flip-flops? I looked in the datasheet, but couldn't find these figures. The clock to ouput times and so forth were listed, but not this specific setup time. The timing analyzer also didn't give me a satisfying result.
Thanks a lot for your reply, Berk Birand