Problem usign xilfatfs...

Marco Albero wrote:

PARAMETER VERSION = 2.1.0

PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = I PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = O PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, VEC = [6:0], DIR = O PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, VEC = [15:0], DIR = IO PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I PORT fpga_0_Ethernet_MAC_slew1_pin = net_vcc, DIR = O PORT fpga_0_Ethernet_MAC_slew2_pin = net_vcc, DIR = O PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin = fpga_0_Ethernet_MAC_PHY_rst_n, DIR = O PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs, DIR = I PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col, DIR = I PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data, DIR = O, VEC = [3:0] PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en, DIR = O PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk, DIR = I PORT fpga_0_Ethernet_MAC_PHY_tx_er_pin = fpga_0_Ethernet_MAC_PHY_tx_er, DIR = O PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er, DIR = I PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk, DIR = I PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv, DIR = I PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data, DIR = I, VEC = [3:0] PORT fpga_0_Ethernet_MAC_PHY_Mii_clk_pin = fpga_0_Ethernet_MAC_PHY_Mii_clk, DIR = IO PORT fpga_0_Ethernet_MAC_PHY_Mii_data_pin = fpga_0_Ethernet_MAC_PHY_Mii_data, DIR = IO PORT fpga_0_DDR_SDRAM_64Mx64_DDR_Clk_pin = fpga_0_DDR_SDRAM_64Mx64_DDR_Clk, DIR = O, VEC = [0:3] PORT fpga_0_DDR_SDRAM_64Mx64_DDR_Clkn_pin = fpga_0_DDR_SDRAM_64Mx64_DDR_Clkn, DIR = O, VEC = [0:2] PORT fpga_0_DDR_SDRAM_64Mx64_DDR_Addr_pin = fpga_0_DDR_SDRAM_64Mx64_DDR_Addr, DIR = O, VEC = [0:12] PORT fpga_0_DDR_SDRAM_64Mx64_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_64Mx64_DDR_BankAddr, DIR = O, VEC = [0:1] PORT fpga_0_DDR_SDRAM_64Mx64_DDR_CASn_pin = fpga_0_DDR_SDRAM_64Mx64_DDR_CASn, DIR = O PORT fpga_0_DDR_SDRAM_64Mx64_DDR_CKE_pin = fpga_0_DDR_SDRAM_64Mx64_DDR_CKE, DIR = O, VEC = [0:0] PORT fpga_0_DDR_SDRAM_64Mx64_DDR_CSn_pin = fpga_0_DDR_SDRAM_64Mx64_DDR_CSn, DIR = O, VEC = [0:0] # PORT fpga_0_DDR_SDRAM_64Mx64_DDR_CKE_pin = fpga_0_DDR_SDRAM_64Mx64_DDR_CKE, DIR = OUT, VEC = [0:1] # PORT fpga_0_DDR_SDRAM_64Mx64_DDR_CSn_pin = fpga_0_DDR_SDRAM_64Mx64_DDR_CSn, DIR = OUT, VEC = [0:1] PORT fpga_0_DDR_SDRAM_64Mx64_DDR_RASn_pin = fpga_0_DDR_SDRAM_64Mx64_DDR_RASn, DIR = O PORT fpga_0_DDR_SDRAM_64Mx64_DDR_WEn_pin = fpga_0_DDR_SDRAM_64Mx64_DDR_WEn, DIR = O PORT fpga_0_DDR_SDRAM_64Mx64_DDR_DM_pin = fpga_0_DDR_SDRAM_64Mx64_DDR_DM, DIR = O, VEC = [0:7] PORT fpga_0_DDR_SDRAM_64Mx64_DDR_DQS_pin = fpga_0_DDR_SDRAM_64Mx64_DDR_DQS, DIR = IO, VEC = [0:7] PORT fpga_0_DDR_SDRAM_64Mx64_DDR_DQ_pin = fpga_0_DDR_SDRAM_64Mx64_DDR_DQ, DIR = IO, VEC = [0:63] PORT sys_clk_pin = dcm_clk_s, DIR = I PORT sys_rst_pin = sys_rst_s, DIR = I # tie unsued pins PORT fpga_0_DDR_SDRAM_64Mx64_DDR_ADDR13_pin = net_gnd, DIR = O PORT FORCE_VREF_IN = vref_fix, DIR = I, VEC = [3:0] PORT FORCE_VREF_OUT = vref_fix, DIR = O, VEC = [3:0]

BEGIN ppc405 PARAMETER INSTANCE = ppc405_0 PARAMETER HW_VER = 2.00.c BUS_INTERFACE DPLB = plb BUS_INTERFACE IPLB = plb BUS_INTERFACE JTAGPPC = jtagppc_0_0 PORT PLBCLK = sys_clk_s PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ PORT RSTC405RESETCHIP = RSTC405RESETCHIP PORT RSTC405RESETCORE = RSTC405RESETCORE PORT RSTC405RESETSYS = RSTC405RESETSYS PORT CPMC405CLOCK = sys_clk_s END

BEGIN ppc405 PARAMETER INSTANCE = ppc405_1 PARAMETER HW_VER = 2.00.c BUS_INTERFACE JTAGPPC = jtagppc_0_1 END

BEGIN jtagppc_cntlr PARAMETER INSTANCE = jtagppc_0 PARAMETER HW_VER = 2.00.a BUS_INTERFACE JTAGPPC0 = jtagppc_0_0 BUS_INTERFACE JTAGPPC1 = jtagppc_0_1 END

BEGIN proc_sys_reset PARAMETER INSTANCE = reset_block PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 0 PORT Ext_Reset_In = sys_rst_s PORT Slowest_sync_clk = sys_clk_s PORT Chip_Reset_Req = C405RSTCHIPRESETREQ PORT Core_Reset_Req = C405RSTCORERESETREQ PORT System_Reset_Req = C405RSTSYSRESETREQ PORT Rstc405resetchip = RSTC405RESETCHIP PORT Rstc405resetcore = RSTC405RESETCORE PORT Rstc405resetsys = RSTC405RESETSYS PORT Bus_Struct_Reset = sys_bus_reset PORT Dcm_locked = dcm_1_lock END

BEGIN plb_v34 PARAMETER INSTANCE = plb PARAMETER HW_VER = 1.02.a PARAMETER C_DCR_INTFCE = 0 PARAMETER C_EXT_RESET_HIGH = 1 PORT SYS_Rst = sys_bus_reset PORT PLB_Clk = sys_clk_s END

BEGIN opb_sysace PARAMETER INSTANCE = SysACE_CompactFlash PARAMETER HW_VER = 1.00.b PARAMETER C_MEM_WIDTH = 16 PARAMETER C_BASEADDR = 0x78060000 PARAMETER C_HIGHADDR = 0x7806ffff BUS_INTERFACE SOPB = opb PORT OPB_Clk = sys_clk_s PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ END

BEGIN opb_v20 PARAMETER INSTANCE = opb PARAMETER HW_VER = 1.10.b PARAMETER C_EXT_RESET_HIGH = 1 PORT SYS_Rst = sys_bus_reset PORT OPB_Clk = sys_clk_s END

BEGIN plb2opb_bridge PARAMETER INSTANCE = plb2opb PARAMETER HW_VER = 1.01.a PARAMETER C_DCR_INTFCE = 0 PARAMETER C_NUM_ADDR_RNG = 1 PARAMETER C_RNG0_BASEADDR = 0x84000000 PARAMETER C_RNG0_HIGHADDR = 0x8400ffff BUS_INTERFACE SPLB = plb BUS_INTERFACE MOPB = opb PORT PLB_Clk = sys_clk_s PORT OPB_Clk = sys_clk_s END

BEGIN opb_uartlite PARAMETER INSTANCE = RS232_Uart_1 PARAMETER HW_VER = 1.00.b PARAMETER C_BAUDRATE = 9600 PARAMETER C_DATA_BITS = 8 PARAMETER C_ODD_PARITY = 0 PARAMETER C_USE_PARITY = 0 PARAMETER C_CLK_FREQ = 100000000 PARAMETER C_BASEADDR = 0x84000000 PARAMETER C_HIGHADDR = 0x84000fff BUS_INTERFACE SOPB = opb PORT OPB_Clk = sys_clk_s PORT RX = fpga_0_RS232_Uart_1_RX PORT TX = fpga_0_RS232_Uart_1_TX END

BEGIN plb_ethernet PARAMETER INSTANCE = Ethernet_MAC PARAMETER HW_VER = 1.01.a PARAMETER C_DMA_PRESENT = 1 PARAMETER C_IPIF_FIFO_DEPTH = 32768 PARAMETER C_PLB_CLK_PERIOD_PS = 10000 PARAMETER C_BASEADDR = 0x84010000 PARAMETER C_HIGHADDR = 0x8401ffff BUS_INTERFACE SPLB = plb PORT PLB_Clk = sys_clk_s PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk PORT PHY_tx_er = fpga_0_Ethernet_MAC_PHY_tx_er PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data PORT PHY_Mii_clk = fpga_0_Ethernet_MAC_PHY_Mii_clk PORT PHY_Mii_data = fpga_0_Ethernet_MAC_PHY_Mii_data END

BEGIN plb_ddr PARAMETER INSTANCE = DDR_SDRAM_64Mx64 PARAMETER HW_VER = 1.11.a PARAMETER C_PLB_CLK_PERIOD_PS = 10000 PARAMETER C_INCLUDE_BURST_CACHELN_SUPPORT = 0 # For the single Rank parts, only use a single bank. # You also need to change the sdram_cke,_csn to a single # bit wide and remove the extra pin from the .ucf file # (remove the (1) pin) PARAMETER C_NUM_BANKS_MEM = 1 # PARAMETER C_NUM_BANKS_MEM = 2 PARAMETER C_ECC_DEFAULT_ON = 0 PARAMETER C_REG_DIMM = 0 PARAMETER C_DDR_TMRD = 10000 PARAMETER C_DDR_TWR = 15000 PARAMETER C_DDR_TRAS = 60000 PARAMETER C_DDR_TRC = 90000 PARAMETER C_DDR_TRFC = 100000 PARAMETER C_DDR_TRCD = 30000 PARAMETER C_DDR_TRRD = 20000 PARAMETER C_DDR_TRP = 30000 PARAMETER C_DDR_TREFC = 70300000 PARAMETER C_DDR_AWIDTH = 13 PARAMETER C_DDR_COL_AWIDTH = 9 # PARAMETER C_DDR_COL_AWIDTH = 10 PARAMETER C_DDR_BANK_AWIDTH = 2 PARAMETER C_NUM_CLK_PAIRS = 4 # Cas latency of 3 of smaller DDRs PARAMETER C_DDR_CAS_LAT = 2 # For a single rank, there is only one memory # space PARAMETER C_MEM0_BASEADDR = 0x00000000 PARAMETER C_MEM0_HIGHADDR = 0x07ffffff # PARAMETER C_MEM0_BASEADDR = 0x00000000 # PARAMETER C_MEM0_HIGHADDR = 0x0fffffff # PARAMETER C_MEM1_BASEADDR = 0x10000000 # PARAMETER C_MEM1_HIGHADDR = 0x1fffffff PARAMETER C_DDR_DWIDTH = 64 BUS_INTERFACE SPLB = plb PORT PLB_Clk = sys_clk_s PORT DDR_Addr = fpga_0_DDR_SDRAM_64Mx64_DDR_Addr PORT DDR_BankAddr = fpga_0_DDR_SDRAM_64Mx64_DDR_BankAddr PORT DDR_CASn = fpga_0_DDR_SDRAM_64Mx64_DDR_CASn PORT DDR_CKE = fpga_0_DDR_SDRAM_64Mx64_DDR_CKE PORT DDR_CSn = fpga_0_DDR_SDRAM_64Mx64_DDR_CSn PORT DDR_RASn = fpga_0_DDR_SDRAM_64Mx64_DDR_RASn PORT DDR_WEn = fpga_0_DDR_SDRAM_64Mx64_DDR_WEn PORT DDR_DM = fpga_0_DDR_SDRAM_64Mx64_DDR_DM PORT DDR_DQS = fpga_0_DDR_SDRAM_64Mx64_DDR_DQS PORT DDR_DQ = fpga_0_DDR_SDRAM_64Mx64_DDR_DQ PORT DDR_Clk = fpga_0_DDR_SDRAM_64Mx64_DDR_Clk PORT DDR_Clkn = fpga_0_DDR_SDRAM_64Mx64_DDR_Clkn PORT Clk90_in = clk_90_s PORT Clk90_in_n = clk_90_n_s PORT PLB_Clk_n = sys_clk_n_s PORT DDR_Clk90_in = ddr_clk_90_s PORT DDR_Clk90_in_n = ddr_clk_90_n_s END

BEGIN plb_bram_if_cntlr PARAMETER INSTANCE = plb_bram_if_cntlr_1 PARAMETER HW_VER = 1.00.b PARAMETER c_plb_clk_period_ps = 10000 PARAMETER c_baseaddr = 0xfffe0000 PARAMETER c_highaddr = 0xffffffff BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port BUS_INTERFACE SPLB = plb PORT PLB_Clk = sys_clk_s END

BEGIN bram_block PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram PARAMETER HW_VER = 1.00.a PARAMETER C_MEMSIZE = 131072 PARAMETER C_PORT_DWIDTH = 64 PARAMETER C_NUM_WE = 8 PARAMETER C_PORT_AWIDTH = 13 BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port END

BEGIN dcm_module PARAMETER INSTANCE = dcm_0 PARAMETER HW_VER = 1.00.a PARAMETER C_CLK0_BUF = TRUE PARAMETER C_CLK180_BUF = TRUE PARAMETER C_CLK270_BUF = TRUE PARAMETER C_CLK90_BUF = TRUE PARAMETER C_CLKIN_PERIOD = 10.000 PARAMETER C_CLK_FEEDBACK = 1X PARAMETER C_EXT_RESET_HIGH = 1 PORT CLKIN = dcm_clk_s PORT CLK0 = sys_clk_s PORT CLK90 = clk_90_s PORT CLK180 = sys_clk_n_s PORT CLK270 = clk_90_n_s PORT CLKFB = sys_clk_s PORT RST = net_gnd PORT LOCKED = dcm_0_lock END

BEGIN dcm_module PARAMETER INSTANCE = dcm_1 PARAMETER HW_VER = 1.00.a PARAMETER C_CLK0_BUF = TRUE PARAMETER C_CLK270_BUF = TRUE PARAMETER C_CLK90_BUF = TRUE PARAMETER C_CLKIN_PERIOD = 10.000000 PARAMETER C_CLK_FEEDBACK = 1X PARAMETER C_EXT_RESET_HIGH = 0 PORT CLKIN = clk_90_s PORT CLK90 = ddr_clk_90_s PORT CLK270 = ddr_clk_90_n_s PORT CLK0 = dcm_1_FB PORT CLKFB = dcm_1_FB PORT RST = dcm_0_lock PORT LOCKED = dcm_1_lock END

PARAMETER VERSION = 2.2.0

BEGIN OS PARAMETER OS_NAME = standalone PARAMETER OS_VER = 1.00.a PARAMETER PROC_INSTANCE = ppc405_0 PARAMETER STDIN = RS232_Uart_1 PARAMETER STDOUT = RS232_Uart_1 END

BEGIN OS PARAMETER OS_NAME = standalone PARAMETER OS_VER = 1.00.a PARAMETER PROC_INSTANCE = ppc405_1 END

BEGIN PROCESSOR PARAMETER DRIVER_NAME = cpu_ppc405 PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = ppc405_0 PARAMETER COMPILER = powerpc-eabi-gcc PARAMETER ARCHIVER = powerpc-eabi-ar PARAMETER CORE_CLOCK_FREQ_HZ = 100000000 END

BEGIN PROCESSOR PARAMETER DRIVER_NAME = cpu_ppc405 PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = ppc405_1 PARAMETER COMPILER = powerpc-eabi-gcc PARAMETER ARCHIVER = powerpc-eabi-ar END

BEGIN DRIVER PARAMETER DRIVER_NAME = sysace PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = SysACE_CompactFlash END

BEGIN DRIVER PARAMETER DRIVER_NAME = plbarb PARAMETER DRIVER_VER = 1.01.a PARAMETER HW_INSTANCE = plb END

BEGIN DRIVER PARAMETER DRIVER_NAME = plb2opb PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = plb2opb END

BEGIN DRIVER PARAMETER DRIVER_NAME = opbarb PARAMETER DRIVER_VER = 1.02.a PARAMETER HW_INSTANCE = opb END

BEGIN DRIVER PARAMETER DRIVER_NAME = uartlite PARAMETER DRIVER_VER = 1.01.a PARAMETER HW_INSTANCE = RS232_Uart_1 END

BEGIN DRIVER PARAMETER DRIVER_NAME = ddr PARAMETER DRIVER_VER = 1.00.b PARAMETER HW_INSTANCE = DDR_SDRAM_64Mx64 END

BEGIN DRIVER PARAMETER DRIVER_NAME = generic PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = jtagppc_0 END

BEGIN DRIVER PARAMETER DRIVER_NAME = bram PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = plb_bram_if_cntlr_1 END

BEGIN DRIVER PARAMETER DRIVER_NAME = emac PARAMETER DRIVER_VER = 1.00.e PARAMETER HW_INSTANCE = Ethernet_MAC END

BEGIN LIBRARY PARAMETER LIBRARY_NAME = lwip PARAMETER LIBRARY_VER = 2.00.a PARAMETER PROC_INSTANCE = ppc405_0 PARAMETER EMAC_INSTANCES = ((Ethernet_MAC,0x00,0x11,0x22,0x33,0x44,0x55)) END

BEGIN LIBRARY PARAMETER LIBRARY_NAME = xilfatfs PARAMETER LIBRARY_VER = 1.00.a PARAMETER PROC_INSTANCE = ppc405_0 END

If you look in your MHS, the plb2opb bridge only allows addresses

0x8400_0000 to 0x8400_ffff through to the OPB. Since opb_sysace has a different address map, it will not be addressable by the processor.

-Siva

Marco Albero wrote: