Field-Programmable Gate Arrays

ISE 9.1i - Process Map Fail without any Error messages

I am using ISE 9.1i. I am getting an error in the Map process which says " Process MAP Fail" without showing any errors...

3 comments posted 19yrs

posted by vnaveen2383

3 comments posted 19yrs posted by vnaveen2383

Virtex-II Pro Flip-Flop Setup time

Hi, For our VHDL design, we are using an evaluation board that has a Xilinx Virtex-II Pro chip on it. The design calls...

4 comments posted 19yrs

posted by dont

4 comments posted 19yrs posted by dont

slave serial configuration of Vertex FPGA using a microcontroller

hi I want to configure a vertex FPGA using a PIC microcontroller in the slave serial mode . I am simply doing the follo...

2 comments posted 19yrs

posted by ramaarchana

2 comments posted 19yrs posted by ramaarchana

configuring vertex4 FPGA

hi i want to configure a XC4 series of vertex 4 FPGA using a micro controller. which bitgen file is to be ussed for def...

1 comments posted 19yrs

posted by ramaarchana

1 comments posted 19yrs posted by ramaarchana

DDR SDRAM simulation model, ML300, Infineon

Hello all, I m working on an application using DDR SDRAM and i want to simulate (timing simulation) the DDR SDRAM worki...

6 comments posted 19yrs

posted by narashimanc

6 comments posted 19yrs posted by narashimanc

Synplify Problem

I am using Synplicity Synplify Premiere 8.8 and I ran into the problem that it keeps retiming my designs such that a gr...

7 comments posted 19yrs

posted by mdhicks2

7 comments posted 19yrs posted by mdhicks2

A Way for a DSP to tell an FPGA to load itself from Flash

Hi, my setup is as follows: 1) DSP ADSP-21065L 2) Xilinx xc3s250 3) Intel JS2BF320J3D Flash I am able to have the DSP l...

5 comments posted 19yrs

posted by axr0284

5 comments posted 19yrs posted by axr0284

Problem usign xilfatfs...

I'm trying to get some files of the CF in a XUP board with a VirtexII-pro FPGA, the problem is that I use 'opb_sysace'...

3 comments posted 19yrs

posted by periket2000

3 comments posted 19yrs posted by periket2000

Error message in ModelSIM PE

Does anyone know what the following error in ModelSIM means? # Loading work.dsss_modem_cosim(structural) # Loading work...

2 comments posted 19yrs

posted by naude.jaco

2 comments posted 19yrs posted by naude.jaco

regarding post place and route timing simulation steps........

hi all, i wanted to do the post place and route timing simulation in modelsim. i have got the files form the xilinx ise...

3 comments posted 19yrs

posted by ekavirsrikanth

3 comments posted 19yrs posted by ekavirsrikanth

Spartan3A : timing Constraints / DCM Outputs

Hi Folks, have the following problem and couldn't found out yet how to solve it: I have a clock input CLK_A and a DCM....

3 comments posted 19yrs

posted by metinnn

3 comments posted 19yrs posted by metinnn

The delay time of coregen Multiplier in Modelsim

I am using the coregen multiplier. I pre-set the parameters to make the o output latency is 0. Why I simulate it in Mode...

0 comments posted 19yrs

posted by threeinchnail

0 comments posted 19yrs posted by threeinchnail

Adding a bram block to a user defined bram controller

Hi all, We have made a bram controller connected to opb bus now we have to connect a bram block to this controller but t...

0 comments posted 19yrs

posted by kahnani

0 comments posted 19yrs posted by kahnani

Re: ESR Meter - Roll your own - ESRrev0.JPG

> John Lark >> Something roughly like this, maybe. This is a 2-minute hack, so >> don't jump all over it right away; a...

34 comments posted 19yrs

posted by No

34 comments posted 19yrs posted by No

LiveDesign, Altium [opinion]

Hi, Does anyone have experience with Altium LiveDesign (Xilinx Spartan-3 XC3S1000) ? How does it perform with ISE WebPa...

5 comments posted 19yrs

posted by jarek.rozanski

5 comments posted 19yrs posted by jarek.rozanski