Field-Programmable Gate Arrays

QuartusII Web Edition software question

Hi All, I am new to Quartus II, and am trying to run a functional simulation. I am using the "Vector Waveform Editor" a...

3 comments posted 19yrs

posted by Kiran.Karra

3 comments posted 19yrs posted by Kiran.Karra

QDR II SRAM Interface

Hi I am currently designing a circuit with a Virtex 4 FX FPGA and QDR I memory chip operating at 250MHz. I have a coupl...

1 comments posted 19yrs

posted by maxascent

1 comments posted 19yrs posted by maxascent

spartan-3e idcode

Hi all, I've recently built a prototype board using a xilinx xc3s250e- ft256. The idcode read back through jtag is not...

11 comments posted 19yrs

posted by jonpry

11 comments posted 19yrs posted by jonpry

[ISE] How to create and map user library in command-line?

Dear I need to "make a script (or batch file) for ISE tool" in order to "crate and map" user libraries". My VHDL code l...

6 comments posted 19yrs

posted by pasacco

6 comments posted 19yrs posted by pasacco

DCM CLK driving load problem

hi , i have a probelm while i am using the DCM for clock mutiply. i am using single DCM for my virtex 2 pro device. i h...

1 comments posted 19yrs

posted by ekavirsrikanth

1 comments posted 19yrs posted by ekavirsrikanth

Which embedded O/S for a 32-bit RISC microcontroller?

My company may soon have to put together our first embedded system. Since we're beginners, we're probably not going to...

6 comments posted 19yrs

posted by cla

6 comments posted 19yrs posted by cla

Image Resolution Rescaling

Hello, I have to do some video scaling on 24-bit video for a 8-bit video dac and am looking for some help in scaling th...

5 comments posted 19yrs

posted by jjlindula

5 comments posted 19yrs posted by jjlindula

What is the resistance of a big FPGA for VCCINT (unpowered)

I've just got a brand new board with a Stratix II S180 on it. Before I power it on, I checked the power supply rails fo...

15 comments posted 19yrs

posted by Marc.Battyani

15 comments posted 19yrs posted by Marc.Battyani

Seeing failures when clocking system-synchronous inter-FPGA interfaces at lower clock rates

My setup has two Xilinx FPGA's which communicate with one another through two unidirectional system-synchronous interfa...

3 comments posted 19yrs

posted by bwilson79

3 comments posted 19yrs posted by bwilson79

Newbie's first FPGA board !

Hello, I have used a FPGA module, XPS, microblaze, verilog etc for a personal project. This was very interesting and no...

17 comments posted 19yrs

posted by lists

17 comments posted 19yrs posted by lists

Xilinx V4 Custom IP

I am trying to write a simple custom IP to get started. I just want to control the LED on my evaluation board. I want t...

0 comments posted 19yrs

posted by SWAmdata

0 comments posted 19yrs posted by SWAmdata

Counter ?

Hello, I require a counter which counts up on positive clock; can be reset to zero upon a reset signal; will stop count...

32 comments posted 19yrs

posted by <miche>

32 comments posted 19yrs posted by <miche>

Re: highly-parallel highspeed connection between two FPGA boards

>Tanks for your answers so far! > >Oay, to make it more precise: I'm looking for an interconnect system >(multi-channel...

1 comments posted 19yrs

posted by robert.ingham

1 comments posted 19yrs posted by robert.ingham

Help with Libero IDE and Verilog...

Hi all, I recently purchased the Actel Fusion Starter Kit. I'm new to both Libero IDE and Verilog and was hoping for so...

2 comments posted 19yrs

posted by weg22

2 comments posted 19yrs posted by weg22

CML output swing for V5

I am using V5 GTP. As per my understanding, the GTP output should swing between 1.2V and 700mV and common mode voltage...

13 comments posted 19yrs

posted by

13 comments posted 19yrs posted by