Latest threads in Field-Programmable Gate Arrays

Microblaze V4 / FSL2.0 - putfsl_interruptable() not working reliably

Hello, I have build a system consisting of two Microblazes connected with an FSL channel. When using the putfsl_interru...

2 19yrs

ahnews

2 19yrs ahnews

Timing in Modelsim

Hello, I'm trying to simulate my design in modelsim and i'm trying to find out if it is possible to choose the set_up d...

3 19yrs

roche.alexis

3 19yrs roche.alexis

QuartusII Web Edition software question

Hi All, I am new to Quartus II, and am trying to run a functional simulation. I am using the "Vector Waveform Editor" a...

3 19yrs

Kiran.Karra

3 19yrs Kiran.Karra

QDR II SRAM Interface

Hi I am currently designing a circuit with a Virtex 4 FX FPGA and QDR I memory chip operating at 250MHz. I have a coupl...

1 19yrs

maxascent

1 19yrs maxascent

spartan-3e idcode

Hi all, I've recently built a prototype board using a xilinx xc3s250e- ft256. The idcode read back through jtag is not...

11 19yrs

jonpry

11 19yrs jonpry

[ISE] How to create and map user library in command-line?

Dear I need to "make a script (or batch file) for ISE tool" in order to "crate and map" user libraries". My VHDL code l...

6 19yrs

pasacco

6 19yrs pasacco

DCM CLK driving load problem

hi , i have a probelm while i am using the DCM for clock mutiply. i am using single DCM for my virtex 2 pro device. i h...

1 19yrs

ekavirsrikanth

1 19yrs ekavirsrikanth

Which embedded O/S for a 32-bit RISC microcontroller?

My company may soon have to put together our first embedded system. Since we're beginners, we're probably not going to...

6 19yrs

cla

6 19yrs cla

Image Resolution Rescaling

Hello, I have to do some video scaling on 24-bit video for a 8-bit video dac and am looking for some help in scaling th...

5 19yrs

jjlindula

5 19yrs jjlindula

What is the resistance of a big FPGA for VCCINT (unpowered)

I've just got a brand new board with a Stratix II S180 on it. Before I power it on, I checked the power supply rails fo...

15 19yrs

Marc.Battyani

15 19yrs Marc.Battyani

Seeing failures when clocking system-synchronous inter-FPGA interfaces at lower clock rates

My setup has two Xilinx FPGA's which communicate with one another through two unidirectional system-synchronous interfa...

3 19yrs

bwilson79

3 19yrs bwilson79

Newbie's first FPGA board !

Hello, I have used a FPGA module, XPS, microblaze, verilog etc for a personal project. This was very interesting and no...

17 19yrs

lists

17 19yrs lists

Xilinx V4 Custom IP

I am trying to write a simple custom IP to get started. I just want to control the LED on my evaluation board. I want t...

0 19yrs

SWAmdata

0 19yrs SWAmdata

Counter ?

Hello, I require a counter which counts up on positive clock; can be reset to zero upon a reset signal; will stop count...

32 19yrs

<miche>

32 19yrs <miche>

Re: highly-parallel highspeed connection between two FPGA boards

>Tanks for your answers so far! > >Oay, to make it more precise: I'm looking for an interconnect system >(multi-channel...

1 19yrs

robert.ingham

1 19yrs robert.ingham

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