Field-Programmable Gate Arrays

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Reconfiguration of a XUP Board

I am using a XUP development board for my project. It is this one: http://www.digilentinc.com/Products/Detail.cfm?Nav1=...
1 comments posted 18yrs
posted by sego
1 comments posted 18yrs posted by sego

PCB Impedance Control

Hi If I am designing a pcb using impedance controlled layers can I treat th power planes as a reference layer as well as...
50 comments posted 18yrs
posted by maxascent
50 comments posted 18yrs posted by maxascent

modelsim

Hai all, Can any one suggest with an example how to run c++ code in modelsim simulator...I didnt understand the example...
5 comments posted 18yrs
posted by fazulu.vlsi
5 comments posted 18yrs posted by fazulu.vlsi

Spartan3E and DDR termination

Hi all, We are building a board with Spartan3E (XC3S1200E FG320) and a 64MB x16 DDR (HYB25DC512160CF-6). Trying to make...
9 comments posted 18yrs
posted by ales.gorkic
9 comments posted 18yrs posted by ales.gorkic

Xilinx FPGA Based Board Problem

Hi All, I am new to FPGAs and my main interest is implementation of some signal processing algorithms on FPGAs. For tes...
3 comments posted 18yrs
posted by piyushkaul
3 comments posted 18yrs posted by piyushkaul

SDF File basics

What does SDF, and Back-annotation/Forward annotation mean? How is an SDF File generated and by which tool? Can someone...
2 comments posted 18yrs
posted by asic1234
2 comments posted 18yrs posted by asic1234

Output signals not synchronized

I have 23bit wide RAM that I use as ROM inferred from the code. When I use the logic analyser (Agilent 16903A) with the...
9 comments posted 18yrs
posted by maricic
9 comments posted 18yrs posted by maricic

Registered output for Altera on-chip memory

When generating a memory block for an Altera Stratix chip using the Megafunction generator, the tool defaults to regist...
1 comments posted 18yrs
posted by edmond.cote
1 comments posted 18yrs posted by edmond.cote

PCIe question

The lane signals should be AC coupled: a. on the motherboard between the controller and PCIe socket b. on the PCIe card...
9 comments posted 18yrs
posted by vsurducan
9 comments posted 18yrs posted by vsurducan

OSERDES behavior

Hello, I'm trying to understand exactly what the behavior of the OSERDES is ... I'm using a 4:1 DDR mode for both data...
0 comments posted 18yrs
posted by SomeOne
0 comments posted 18yrs posted by SomeOne

memory in spartan 3 fpga

Hi, I'd like to set up block rams(16k) to acts as a ROM lookup table after initialization. After establishing the Memor...
2 comments posted 18yrs
posted by vkmselva
2 comments posted 18yrs posted by vkmselva

intialize memory in fpga

I'd like to set up block rams(16k) to acts as a ROM lookup table after initialization. After establishing the Memory Ar...
3 comments posted 18yrs
posted by vkmselva
3 comments posted 18yrs posted by vkmselva