Latest threads in Field-Programmable Gate Arrays

An FPGA startup is seeking testcase from potential customers

Hello, Silicon Blue Technologies is an FPGA startup located in Sunnyvale CA. The FPGA product it is developing has ultr...

4 19yrs

siliconbluetechnology

4 19yrs siliconbluetechnology

Die size, pitch size?

Dear When I look at Virtex-II Pro data sheet (DS083 v. 4.5), page 7, I see following table. ------------------------- P...

13 19yrs

pasacco

13 19yrs pasacco

Reconfiguration of a XUP Board

I am using a XUP development board for my project. It is this one: http://www.digilentinc.com/Products/Detail.cfm?Nav1=...

1 19yrs

sego

1 19yrs sego

PCB Impedance Control

Hi If I am designing a pcb using impedance controlled layers can I treat th power planes as a reference layer as well as...

50 19yrs

maxascent

50 19yrs maxascent

Spartan 3E starter kit (Rev.D) modification : 3E500 -> 3E1200

Hello! I would like to change the FPGA in this board to a bigger one, but I don't know if it's possible. I noticed in t...

3 19yrs

dormanpeter1

3 19yrs dormanpeter1

modelsim

Hai all, Can any one suggest with an example how to run c++ code in modelsim simulator...I didnt understand the example...

5 19yrs

fazulu.vlsi

5 19yrs fazulu.vlsi

Spartan3E and DDR termination

Hi all, We are building a board with Spartan3E (XC3S1200E FG320) and a 64MB x16 DDR (HYB25DC512160CF-6). Trying to make...

9 19yrs

ales.gorkic

9 19yrs ales.gorkic

Xilinx FPGA Based Board Problem

Hi All, I am new to FPGAs and my main interest is implementation of some signal processing algorithms on FPGAs. For tes...

3 19yrs

piyushkaul

3 19yrs piyushkaul

Where is Command Reg and Status Reg as mentioned in PCI system architecture (Mindshare) in generated pci32 core?

Hi, I realize that in cfg.vhd files generated by PCI32 LogiCore does not have command register and status register. Fro...

3 19yrs

yasirmm

3 19yrs yasirmm

SDF File basics

What does SDF, and Back-annotation/Forward annotation mean? How is an SDF File generated and by which tool? Can someone...

2 19yrs

asic1234

2 19yrs asic1234

Output signals not synchronized

I have 23bit wide RAM that I use as ROM inferred from the code. When I use the logic analyser (Agilent 16903A) with the...

9 19yrs

maricic

9 19yrs maricic

Difference in the JTAG instructions between Virtex and Virtex II

Hi, I am writing a C/C++ driver for programming a Virtex 2 using the JTAG port (Parallel III cable) since it's required...

0 19yrs

shadabambat1

0 19yrs shadabambat1

Registered output for Altera on-chip memory

When generating a memory block for an Altera Stratix chip using the Megafunction generator, the tool defaults to regist...

1 19yrs

edmond.cote

1 19yrs edmond.cote

PCIe question

The lane signals should be AC coupled: a. on the motherboard between the controller and PCIe socket b. on the PCIe card...

9 19yrs

vsurducan

9 19yrs vsurducan

OSERDES behavior

Hello, I'm trying to understand exactly what the behavior of the OSERDES is ... I'm using a 4:1 DDR mode for both data...

0 19yrs

SomeOne

0 19yrs SomeOne

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