Hello,
I'm trying to understand exactly what the behavior of the OSERDES is ... I'm using a 4:1 DDR mode for both data and tristate.
I send clk_2x to CLK and clk_1x to CLK_DIV. (both derived from a PLL on v5 / DCM on v4).
When I look at the behavioral simulation, I don't see the results that I expect from the documentation. And even in the documentation, depending on what page I read, I understand something different ...
So does some one which one is right ? Let say clk_0 has a 10 ns period, clk_2x 5 ns period and that both have rising edge at 0 ns. I set a data[3:0] on the D1-D4 input of OSERDES at t = -2 ns ... when will I see D1 appear on the OQ port ?
- In the virtex 5 useguide page 385 (table 8-9) they say the latency is 1 CLKDIV and 1 CLK. So I would expect the D1 to appear at t = 15 ns ( captured at t=0ns, the first rising edge of CLKDIV after I set the data, then wait 1 CLKDIV cycle, then wait 1 CLK cycle )
- In the virtex 5 userguide page 347 (figure 8-15) I see an example and it would seem I should see D1 at the first edge of CLK after 1 CLKDIV has passed ... So that would be t = 12.5 ns ( captured at t=0ns, the first rising edge of CLKDIV after I set the data, then wait
1 CLKDIV, then the first edge of CLK is a falling one, at 12.5 ns )- When I do a simulation, I see the data at t = 5 ns ...
So can someone shed some light on the situation please ?
Thanks,
Sylvain