Spartan3E and DDR termination

If you're only driving a single chip with very short lines you can probably get away without termination on everything except the clock. I would suggest using SSTL2_I instead of SSTL2_II to avoid overdriving. Another approach is to just leave out the series termination on these signals and just add the parallel termination to Vtt. I've used the latter method with Virtex2 and an SO-DIMM without DCI on the data lines and SSTL2_I drive. A good argument for leaving out the series termination is any net where the driving stub (from the S3 to the resistor) is about the same length as the driven stub (from the resistor to the memory). Here the terminator is of dubious value.

It's probably best to simulate your transmission lines, especially if you're planning to run the memory at its maximum speed of 166 MHz / DDR333. My V2 design ran at

HTH, Gabor

One other thought if your main interest is in reducing the board size. Often I find that using a x32 single-data-rate (143 MHz) memory can save space. If you're using a TSSOP-66 package for the DDR part, the 86-pin TSSOP for the x32 SDR part has the same footprint and runs from +3.3V with no requirements for VREF and DQS pins on the FPGA and no Vtt or 2.5V supply. So unless you already had the 2.5V supply for another reason you could save space, and depending on the number of Vref pins eaten up by the SSTL2 I/O standard, you may not add significantly more I/O pins to the design.

First, I would suggest changing your newsgroup alias to something other than "Guru" if you're asking whether or not you can eliminate terminations. How about "Have Lots To Learn"?

You must meet setup and hold requirements of the data and control lines, meet the rise/fall time and monotonicity requirements of the clocks and strobes, and not violate the overshoot and undershoot specs on all signals for the FPGA and RAM. That's all there is to it.

Get a simulator and determine what you need for your particular FPGA, RAM, and board layout restrictions. If you're going to skimp on the terminations then this is the only way to do it.

Bob

As Gabor suggests, it may be possible to eliminate the series terminations if traces are kept short enough.

If you also want to eliminate the parallel terminations to VTT, consider moving to DDR-II, where you can use the On-Die Termination (ODT) instead. It means a little extra design complexity, and 1.8V supplies, but if space is important enough it may be worth considering.

- Brian

We already considered using a DDR2 since it enables ODT. The only thing I am afraid of is the minimal frequency of 125MHz. This means that carefull FPGA pinout selection is a must (e.g MIG layout). The other problem are huge memory controllers; MCH_OPB_DDR2 takes approx 1500 slices.

What about 8 bit DDR2? This way I can get away with only one FPGA bank and layout to MIG rules. Did anyone used it with MPMC2 (x8 is not supported by MCH_OPB_DDR2)?

Cheers,

Guru

How looks the Vref signal inside the DDR II ? Exactly what is good for ?

thx, Vasile

Not quite sure what you're asking here. The point I was trying to make is that the single-data-rate parts don't need to tie up FPGA pins with Vref and DCI. On Virtex 2 parts, you can have as many as 6 Vref pins in one bank. If you use SSTL2 signalling instead of LVTTL you lose the ability to use these pins as I/O. If you also decide to use DCI you lose an additional 2 pins per bank. The DDR parts also have more control pins (differential clock adds one pin, DQS adds one per 8 bits of interface). So if you can live with the data rates of the single- data-rate parts, you can avoid a lot of headaches and perhaps use only a small number of additional pins to double the data width.

By the way, for SSTL2 you need Vref as a precision threshold reference at 1/2 Vddq, usually 1.25V or 1.3V depending on the speed for DDR I parts. LVTTL allows a wide threshold tolerance, usually 0.8 to 2.0v but generally won't work well at DDR bit rates.

Double check that MPMC2 uses ODT. I'm not sure it does. Otherwise DDR2 is a big win if you are worried about signal integrity. If you've seen a DDR design go wrong, the DDR2 data sheets will make you say, "wow, that would have been handy!" about 100 times.

I have asked how looks the Vref internal circuitry of a DDRAM II. Why you need Vref for DDRAM II and which is the Vref value related to Vtt. I didn't ask about FPGA Vref which description is quite clear to me. It seems from your answer it's about SSTLII standard only, but I'm not sure it's the complet answer. Do you have any datasheet for DDRAM II talking in detail about the Vref problem?

thx, Vasile

The point I was trying to