When generating a memory block for an Altera Stratix chip using the Megafunction generator, the tool defaults to registering the 'q' output port. I am curious, is there a particular reasoning behind this choice? Performance maybe?
Thanks,
-- Edmond
When generating a memory block for an Altera Stratix chip using the Megafunction generator, the tool defaults to registering the 'q' output port. I am curious, is there a particular reasoning behind this choice? Performance maybe?
Thanks,
-- Edmond
Besides the performance there is a benefit of routing as well. You can place your modules farther from the memory blocks. You may have to do this if say you are driving external i/os from the same block that is also accessing the internal ram block.
-sanjay
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