Registered output for Altera on-chip memory

When generating a memory block for an Altera Stratix chip using the Megafunction generator, the tool defaults to registering the 'q' output port. I am curious, is there a particular reasoning behind this choice? Performance maybe?

Thanks,

-- Edmond

Reply to
Edmond Coté
Loading thread data ...

Besides the performance there is a benefit of routing as well. You can place your modules farther from the memory blocks. You may have to do this if say you are driving external i/os from the same block that is also accessing the internal ram block.

-sanjay

Reply to
fpgabuilder

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.