Field-Programmable Gate Arrays

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MG Leonardo Synthesis Options

Hello, does anyone have an answer to the following two issues on using leonardo: 1. How can I see the exact functionali...
1 comments posted 18yrs
posted by giorgos.puiklis
1 comments posted 18yrs posted by giorgos.puiklis

A way to limit the data path delay

Hello, I have a problem with apparently no issue. I use a V5 and I have a problem with the data path delay of a net. Th...
2 comments posted 18yrs
posted by lpaulo07
2 comments posted 18yrs posted by lpaulo07

Minimum Oscillator Frequency

Hallo to everyone, I should develop a system which outputs a pwm signal into a filter to obtain a sine at 500 Hz which...
7 comments posted 18yrs
posted by marcotoschi
7 comments posted 18yrs posted by marcotoschi

Possible CRC error on XC3S400 - now what?

Hi, I'm trying to configure a Xilinx Spartan 3 s400 through JTAG in a new prototype but I'm getting some weird results...
20 comments posted 18yrs
posted by mickeymeeuw
20 comments posted 18yrs posted by mickeymeeuw

4-bit table look-up

Hi I have a simple question, whats the best way of designing a lookup table which is 16 bit wide in VHDL and for sythes...
8 comments posted 18yrs
posted by KMayer
8 comments posted 18yrs posted by KMayer

A video tutorial: The Xilinx FPGA Editor

Hello all, For all those who know that the Xilinx FPGA Editor exists, and maybe that it's good for something, but are r...
3 comments posted 18yrs
posted by eli.billauer
3 comments posted 18yrs posted by eli.billauer

forcing "Unused IOB Pin -> " from .ucf

Hi all, Are there any way to force some generate programming file from .ucf ? 1. Generate Programming File -> General O...
0 comments posted 18yrs
posted by job
0 comments posted 18yrs posted by job

OFFSET In and hold time

Hello, I have a question about the OFFSET In constraint. To my mind, OFFSET In is the same thing that the set-up time....
1 comments posted 18yrs
posted by lpaulo07
1 comments posted 18yrs posted by lpaulo07

Server configuration for Virtex5

Hi, Our company is looking to buy some Linux servers for design implementations of Virtex5. So I was wondering if there...
3 comments posted 18yrs
posted by togoli
3 comments posted 18yrs posted by togoli

Call For Papers: FPL 2008

FPL International Conference on Field Programmable Logic and Applications Call for papers Submission Deadline -- March...
0 comments posted 18yrs
posted by m8pple
0 comments posted 18yrs posted by m8pple

Bitstream verification through readback

Hi, i need to know is it possible to readback and verify the loaded configuration in the FPGA after the GSR is deassert...
5 comments posted 18yrs
posted by sheikh.m.farhan
5 comments posted 18yrs posted by sheikh.m.farhan

Scaling data

Hello All, I am using the UNIFORM procedure in VHDL to generate random numbers. UNIFORM generates random numbers in the...
4 comments posted 18yrs
posted by FPGA.unknown
4 comments posted 18yrs posted by FPGA.unknown

Internal signal names in ModelSim

I have synthesized and implemented my design, and I was going to simulate post-route using ModelSim. The problem is tha...
4 comments posted 18yrs
posted by x
4 comments posted 18yrs posted by x

Loading from Compact Flash on ML310...

Hi everybody, I have written a very simple code for microblaze on Virtex II-Pro (XC2VP30 on ML310 board) which basicall...
3 comments posted 18yrs
posted by amirhossein.gholamipour
3 comments posted 18yrs posted by amirhossein.gholamipour

spartan3a support DVI ?

spartan3a support T.M.D.S. signal standard ,but since DVI signals are 1000M or higher ,how can receive data from DVI ?
3 comments posted 18yrs
posted by huangjielg
3 comments posted 18yrs posted by huangjielg