4-bit table look-up

Thanks for the feedback Eric, but the problem is that the content is not fix. So I cant use a rom as u suggested, I need something that reads the actual content out of a register an applies then the current values

If the values are fixed, it's just a 16x1 ROM (for the single bit case), or 16x32 ROM (32-bit wide case). XST will synthesize something appropriate from any reasonable VHDL construct; see the examples in the XST manual. Here's one way of doing the 32-bit wide case with a concurrent assignment statement:

signal select: std_logic_vector (3 downto 0); signal foo: std_logic_vector (31 downto 0);

foo

Personally I prefer to use case statements for constructs like this to avoid any accidental priority encoding by the synthesis tool.

signal sel: std_logic_vector (3 downto 0); signal foo: std_logic_vector (31 downto 0);

process (sel) case sel is when "0000" foo

Except when designing a 7-segment decoder ;-)

always @ (ibcd) begin case (ibcd) // abcdefg 0 : oseg = 7'b1111110; 1 : oseg = 7'b0110000; 2 : oseg = 7'b1101101; 3 : oseg = 7'b1111001; 4 : oseg = 7'b0110011; 5 : oseg = 7'b1011011; 6 : oseg = 7'b1011111; 7 : oseg = 7'b1110000; 8 : oseg = 7'b1111111; 9 : oseg = 7'b1111011; default : oseg = 0; endcase

That's fine for synthesis, but since the type is std_logic_vector, many simulators will complain that you've left a lot of alternatives unspecified. I suppose adding when others => foo

So it's either a RAM, or a register with a mux. Here's a single-bit wide version of the register with mux.

use IEEE.numeric_std;

signal reg: std_logic_vector (15 downto 0); signal sel: std_logic_vector (3 downto 0);

signal foo: std_logic;

foo