Bitstream verification through readback

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Hi,
i need to know is it possible to readback and verify the loaded
configuration in the FPGA after the GSR is deasserted and the FPGA is
up and running with the loaded configuration? I am suspecting that due
to power requirement of my application, the FPGA loses its
configuration when the current demand increases ( HDD is connected to
the FPGA board, when the FPGA talks to the HDD through SATA
controller, the current goes up from  .8 Amp to 1.7 Amps)and the FPGA
stops working in the expected manner.

Any ideas.........

Farhan



Re: Bitstream verification through readback
Farhan,

First question: whose FPGA?  Not every manufacturer supports readback.

Xilinx FPGAs may be verified while operating, easiest being through the
JTAG cable.

If any of the power supplies droop sufficiently to trigger the power on
reset, then the device will clean out (erase its configuration memory,
and re-load itself).

Such a case it pretty easy to see, by watching the power supply voltages
with an oscilloscope, and also looking at the configuration interface
Done, CCLK, etc.).

Austin

Re: Bitstream verification through readback
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What do the supply voltage do? Does they remain in spec at all times? Is
there any noise on them? What about the voltages on the IO pins, do they
look correct?

If you really think the fpga is getting corrupted or reset somehow,
maybe you could use one pin to blink an LED or something and see if it
ever acts strange.

-Jeff

Re: Bitstream verification through readback
You mention that there is a problem when the current demand increases.
Could it be that you don't have enough bulk capacitance to supply the
instaneous current demand, thus your supplies dip.

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Re: Bitstream verification through readback
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My guess would be low frequency noise on your core or I/O supply, which
can be quite hard to see on a 'scope. Try some very large low ESR
capacitors on the suspect rails to see if that improves matters. As
someone else said, the easiest way to verify is using a cable and
verifying the bitstream.


Dunstan

ByteSnap Design Ltd,
Web:    www.bytesnap.co.uk

Re: Bitstream verification through readback
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Try separate power supplies for the FPGA and HDD ..?


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