Hi, i need to know is it possible to readback and verify the loaded configuration in the FPGA after the GSR is deasserted and the FPGA is up and running with the loaded configuration? I am suspecting that due to power requirement of my application, the FPGA loses its configuration when the current demand increases ( HDD is connected to the FPGA board, when the FPGA talks to the HDD through SATA controller, the current goes up from .8 Amp to 1.7 Amps)and the FPGA stops working in the expected manner.
Any ideas.........
Farhan