Latest threads in Field-Programmable Gate Arrays

Keeping Xilinx tool from Optimizing out Debugging signals

There is a signal that I need to trigger Chipscope on it for debugging purposes. However, after synthesis the signal is...

2 18yrs

mhs000

2 18yrs mhs000

Xilinx timming analysis

Hello, Somebody can explain me what is the "Tdcmino" signal in a DCM ? The "Tdcmino" delay is very high (more than 5 ns)...

2 18yrs

lpaulo07

2 18yrs lpaulo07

Gemac on ML402

Hi, Does anyone run the Gemac on a Xilinx ML402 board ? I try to use the example design that comes with the core but it...

0 18yrs

josue.freitas

0 18yrs josue.freitas

Why use small resistor for Vcco voltage regulator

In Xilinx application notes XAPP457 ( http://www.xilinx.com/support/documentation/application_notes/xapp457.pdf), the r...

11 18yrs

junsong.liao

11 18yrs junsong.liao

Loading the design from Compact Flash...

Hi everybody, It's been a while I'm struggling with ML310 board to have my design loaded from compact flash to the Virt...

6 18yrs

amirhossein.gholamipour

6 18yrs amirhossein.gholamipour

Why does a 36 x 36 Multiplier in a Xilinx Spartan 3E require 9 multipliers?

I'm implementing a 36 bit x 36 bit multiplier with a 72 bit output in a Xilinx Spartan 3E. I've tried to poke down into...

4 18yrs

dale.prather

4 18yrs dale.prather

Low Pin Count (LPC) bus code available?

I'm working on a Low Pin Count (LPC) bus interface and would like to double check my design with an existing implementa...

2 18yrs

johnp3+nospam

2 18yrs johnp3+nospam

question about fsl and microblaze

hi i'm just working on a project where i need to create an fsl interface for my custom ip core. i used the "create and...

3 18yrs

u_stadler

3 18yrs u_stadler

Xpower

Hi All, I am trying to see the power consumption of some design using XPower with ModelSim generated .vcd file I get th...

1 18yrs

charles.wagner

1 18yrs charles.wagner

Design security for pre-Virtex2 parts ?

Hi all, Has anyone ever tried to improve the security for the old Xilinx FPGA devices, which doesn't have the 3-DES encr...

8 18yrs

ccon67

8 18yrs ccon67

iru1209 regulator

Hello all, i have a design finished a few month ago, that is working fine on a xc2s200-pq208, but when i port it to a x...

2 18yrs

walther.zabel

2 18yrs walther.zabel

Xilinx BSCAN primitives proper use

Has anyone managed to get the xilinx BSCAN primitives (for interfacing with the USERx jtag registers/comands) working r...

10 18yrs

jonas

10 18yrs jonas

FPGA in Telecommunications

Hello All, I am curious what are main applications of FPGA in Telecommunications? It's well known (well, at least for s...

7 18yrs

vladimir.v.korostelev

7 18yrs vladimir.v.korostelev

Actel Fusion FPGA

Hello, I am working on Actel Fusion FPGA. I am having problems with the ADC in my design. Can someone please help me wit...

3 18yrs

iamrehman

3 18yrs iamrehman

I need a SDRAM controller

Hi everybody! I did a controller to SRAM, so, I need controller a SDRAM, like it=B4s more difficult, (refresh). I=B4m l...

8 18yrs

dorama2

8 18yrs dorama2

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