Hello,
I have a problem with apparently no issue.
I use a V5 and I have a problem with the data path delay of a net. This net is used everywhere in my design and particulary in fixed blocs. The fanout is reduced to the maximum and I put a maxdelay constraint on it. The syntesis options are configured for speed.
Anybody have an idea to reduce this delay ?
Tk.
There are two normal ways to fix this problem. Firstly to add pipe-lining stages (series flip-flops) in, accepting that this puts a clock delay on the signal. The delay may or may not matter depending on your design.
Alternatively, replicating the logic would help to reduce the fan-out. The latter is something that your synthesis tool may try. This depends on the tool settings, but you should be able to see if it has by looking at the synthesis reports. If you do it manually in the RTL you may be able to do it in a more transparent and controllable and therefore maintainable manner.
Regards,
Dunstan Power
ByteSnap Design Ltd, Web:
I cannot change the logic because this net is used in an IP. In a virtexII there were low skew lines, there is sometning like that in a v5 ??
Tk.
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