Internal signal names in ModelSim

You'll have to hunt for them in the VHDL file that the synthesis tool produced for the post-route design. It's painful, no shortcuts that I know of.

Kevin Jennings

I have completed maybe 40 Xilinx designs in the last 6 years, and have not run a single back annotated simulation.

Good luck.

In general there is none but there are some cases which might be helpful. Usually module ports are preserved so you can put the names you're interested as module outputs and still have them available. They don't even have to be at the top level (usually). The other case is registers are usually quite predictively changed ie a register foo[7:0] almost always gets named foo_reg_7, foo_reg_6 etc. You can use this to access your signals. One question is that why you need to see your internal signals in gate level. Even if you feel the need to do gate-level back-annotated sims, surely you don't need to debug them there unless of course you're trying to catch an apparent incorrectly generated hardware problem but that's very rare and the problem is almost always somewhere else. Debug your circuits in RTL fully and make sure you meet timing in P&R then you don't have to debug gate-level.

Depending on your synthesis tool and place and route tool, there are attributes available such as 'preserve_signal' and 'preserve_driver' that can be used on those special signals you would like to keep. That is, it prevents them from being renamed or optimized out. If there are only a few important signals you need to keep, then this is a good alternative.