Loading from Compact Flash on ML310...

Hi everybody, I have written a very simple code for microblaze on Virtex II-Pro (XC2VP30 on ML310 board) which basically writes something to STD-OUT (through uart). When I load the design to the FPGA through parallel cable IV everything works perfectly which gives me the idea that basically there is nothing wrong with the design in general and the code. I've been trying to load the design through compact flash for a few weeks now but I haven't still been able. I'm using EDK 8.2.02 and ISE 8.2.03. If I generate the .ace file using EDK when I switch on the board the sysAce Error red LED is turned on meaning that the design is not loaded appropriately. However when I generate .ace file using iMPACT from ISE then it sounds like the design is loaded because the green SysAce Status LED is turned on but it writes nothing to the hyperterminal through which I'm getting connected to UART on the board.

Do you have any clue what the problem is?

I appreciate any help beforehand,

Reply to
Xesium
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It sounds like you have a working design since you can download through the PC4 cable and have it run. I am not an EDK expert, but here are my thoughts.

The SystemACE error LED is likely being lit as you have not changed your JTAG chain description to remove the System ACE from the chain. You need System ACE in the chain description when downloading from a cable, but when the System ACE is the master and programming the devices it isn't part of the chain description since it is the master.

In the case of iMPACT generating a valid ACE file but not a working design, this is probably due to the software not being initialized in the BlockRAMs. You should have an ELF file that was generated for your program that was marked to be the one that is initialized to the BlockRAMs and a BMM file that defines the memory map to internal/external RAMs. When you do an "Update Bitstream" these should be combined with the placed/routed BIT file to create a download.bit file. This is the one that you should be using with iMPACT to generate the ACE file.

I hope that this helps.

BTW, 8.2i is fairly old you might also want to consider moving to 9.2i

Ed McGettigan

-- Xilinx Inc.

Reply to
Ed McGettigan

Hi Ed,

Thanks. Actually the problem was solved. But the problem was something else. Previously I used to export my design to ISE and synthesize and place and route it there and then generate the ace file through iMPACT. However this time (that worked) I actually did everything through EDK and used shell commands to generate the ace file. So basically the design through ISE has some problems some where and I have not realized where exactly. I realized that the mode pins (M2M1M0) are set as 101 (boundary-scan) in EDK but the same in ISE were set as 111 (slave serial). I'm not sure but I think 101 is the desired configuration because sysAce is going to reconfigure from compact flash. So there is no external clock to the FPGA configuration unless I'm wrong. (Will you please clarify this issue?) In any case I tried changing the configuration mode in ISE but it didn't work. So I'm not sure what exactly the problem is with ISE but obviously generating the ace file from the design in ISE doesn't work but the same in EDK is working.

Thanks for your information on SysAce. Also the problem with EDK9.2i is that it doesn't support ML310 board that I'm currently working on, so that's the reason that I couldn't use it. But I'm considering moving to ISE 9.1 at least.

Thanks again,

Amir

Reply to
Xesium

This indicates that the JTAG chain was not defined correctly in ISE, but EDK understood which board you were using and defined the chain correctly.

Mode pins are physical items and are set on the board. There is no software that can set these for you.

System ACE requires a clock to operate and generates a JTAG TCK clock to the FPGA chain. Slave Serial mode requires an external clock to be provided that is aligned with the serial data stream.

I do not know why support the ML310 was removed in the latest version of the EDK Base System Builder. EDK can still be used to generate designs for the ML310, but just not through the BSB flow. EDK supports a "rev up" function that should be able to take your old 8.2i design and bring it forward to the 9.2i environment.

Ed McGettigan

-- Xilinx Inc.

Reply to
Ed McGettigan

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