Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15253 Threads Posts
to

Using ICAP in s3a to reconfigure

Hi everybody, I am currently working on the mulitboot feature of xilinx s3a. I have programmed one of the on-board PROM...
1 comments posted 18yrs
posted by kundanmit
1 comments posted 18yrs posted by kundanmit

Hardware Cosim no output

Hi all, I am doing hardware Cosimulation in System Generator via JTAG PLatform USB cable to my ML501 Evaluation kit but...
0 comments posted 18yrs
posted by hilo_pupu
0 comments posted 18yrs posted by hilo_pupu

Synthesis of functions in Quartus

Hello all, I have a bunch of functions I would like to synthesize on Quartus. These are going to be part of a library....
3 comments posted 18yrs
posted by FPGA.unknown
3 comments posted 18yrs posted by FPGA.unknown

sFPDP IP Core

hi, I am quite a newbie with FPGAs and would like some opinion about existing sFPDP IP Cores for serial communications....
0 comments posted 18yrs
posted by jtamahey
0 comments posted 18yrs posted by jtamahey

Xilinx parallel cable 4 clone

Hi, I just purchased Enterpoint's Darnaw1 module. I have Xilinx parallel 3 cable not Parallel 4 cable. Is it possible t...
3 comments posted 18yrs
posted by aramosfet
3 comments posted 18yrs posted by aramosfet

About John Williams' ICAP driver?

Hi everybody, I have successfully integrated the ICAP driver to our Linux on the PPC on the ML310 board. But now I had...
2 comments posted 18yrs
posted by grant0920
2 comments posted 18yrs posted by grant0920

Picoblaze enhencement and assembler

Hi, I wasn't very satisfied with the available assembler, so a few month ago I wrote a new compiler for the Picobaze du...
16 comments posted 18yrs
posted by SomeOne
16 comments posted 18yrs posted by SomeOne

Seed Values

I would like to know how the initialisation of seed values would affect the output of the procedure of UNIFORM. I have...
11 comments posted 18yrs
posted by FPGA.unknown
11 comments posted 18yrs posted by FPGA.unknown

The Java processor JOP is now GPL

Hi all, it has been silent about JOP in this group for a while. However, development is still very active. I've now dec...
0 comments posted 18yrs
posted by mschoebe
0 comments posted 18yrs posted by mschoebe

Command to unzip hardware cosim files

Hi all. I have recently downloaded the driver files in order to do hardware cosim on a ML501 Evaluation kit but I do no...
0 comments posted 18yrs
posted by hilo_pupu
0 comments posted 18yrs posted by hilo_pupu

XEM3010

Hi, i am configurating the PLL of my FPGA board to achieve a higher frequency. The master clock frequency of it is at 1...
0 comments posted 18yrs
posted by raullim7
0 comments posted 18yrs posted by raullim7

canny edge detection

hai.. i am doing project in image processing using cyclone II fpga...i need the core of the canny edge detection for one...
1 comments posted 18yrs
posted by rsvn29
1 comments posted 18yrs posted by rsvn29

Planahead IP export

Hi, I'm trying to insert an IP core generated by PlanAhead into our script-based flow, but map fails with Pack:679 erro...
2 comments posted 18yrs
posted by pato
2 comments posted 18yrs posted by pato