Hi everybody,
I have successfully integrated the ICAP driver to our Linux on the PPC on the ML310 board. But now I had a problem about the ICAP driver. My combinational circuits, such as the very simple adder design and the subtractor design, can successfully be partially reconfigured by the ICAP driver, but the sequential circuit cannot be. Are there any things that I have to consider, such the hardware design? Thanks!
Best regards, Huang
The impact programming tool can download partial bitstreams just like the ICAP driver. So, test your partials there. If they work in impact, but not through ICAP + Linux driver, then it's pretty strange.
It's most likely an issue with the bitstreams themselves - double check how you generated them, and try the partial-reconfig mailing list or other sources of help on the subject (this newsgroup!).
Since you have problems with sequential but not combinational circuits, my first guess would be a reset or clocking problem in your crossing from fixed -> reconfigurable partitions.
Regards,
John
Dear John:
All my partial bittstreams can work in the impact tool. I am not sure what are the reset or clock problems that you menetioned? Does it mean that the HDLs of my hardware designs need to be remodified its reset and clock signals? I followed the EAPR flow so I used a global buffer to connect the clock signal for the PR design. The reset signal is connected to the PR design through the busmacro. Is it right? Or are there other rules that I have to consider? Or does the hwicap APIs that are provied by Xilinx need to be corrected somewhere? Thanks!
Best Regards, Hunag
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