Seed Values

FPGA WITH NO NAME (I prefer to talk to humans),

You should be getting a different sequence. Did you do all of your process steps (save file, recompile, re-run simulation)? Is there a bug in your scaling process?

Just for fun, write a test program that loops while generating random values. How many times does it need to loop before all values are generated? After going through your loop n times where n = range of values, how many values are not covered? I usually track this in an array.

There is the fun stuff. You will have to enumerate what these are and write code to track them. For help you will need to be more specific.

Cheers, Jim

You initialize the seed values once. After that, they are modified by the calls to uniform. You should not change the seed values anymore. Unless you want to repeat the generated random values. Because that is what the seed value guarantees: initialize them with the same values as before, and uniform will generate the exact same numbers as before.

Are you sure?

Something like:

use std.textio.all; ... process is variable l: line; variable rand : integer; (or signed()) variable seed1, seed2: integer; begin seed1 := 123; seed2 := 5678; for i in 1 to 1000 loop rand := your random function, calling uniform() write(l, rand); writeline(output, l); end loop; wait; end process;

the initialisation of seed values would

I have saved, recompiled and rerun simulation. The strange thing is, I am getting the same sequence if I output uniform in real format even after I change the initialisation of Seed1 and Seed2. uniform(S1,S2,rand1); rand_real How many times does it need to loop before all values are generated?

toSigned converts real to signed of specified bw. I dont see any problem with toSigned.

I am dealing with someone who himself doesnt know what he wants. I would just like to write smthg to prove that it works correctly, nothing very particular.

I am very sure. I my top level, I have defined SEED1 and SEED2 (of type positive) as signals and then assigned them to S1 , S2 of type positive.

I just commented my signals SEED1,SEED2 in the top level. I initialised the values of SEED1, SEED2 within the process (not taking as signal inputs as before). Now, I see that I am getting different sequence for different values of SEED1, SEED2. Why would this happen? Shouldnt it behave the same if I have SEED1, SEED2 as signals and then within process I have variable S1,S2 initialised to signal SEED1, SEED2 I dont understand why it behaves so.

Variables update immediately. Signals don't update until they see a wait.

-- Mike Treseler

Thanks a bunch guys. I appreciate your help.

FPGA,

Your simulator should have reported an error when you declared SEED1 and SEED2 as signals as uniform requires them to be variables.

Jim

It did not report error. I had assigned the signals to variables within the process and then passed then to uniform. I am not sure if its a good idea to assign signals to variables (is it a big NO ?)

This is a matter of style. If the signal is used for nothing else, I would eliminate it.

-- Mike Treseler