Field-Programmable Gate Arrays

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canny edge detection

hai.. i am doing project in image processing using cyclone II fpga...i need the core of the canny edge detection for one...
1 comments posted 18yrs
posted by rsvn29
1 comments posted 18yrs posted by rsvn29

Planahead IP export

Hi, I'm trying to insert an IP core generated by PlanAhead into our script-based flow, but map fails with Pack:679 erro...
2 comments posted 18yrs
posted by pato
2 comments posted 18yrs posted by pato

FPGA Editor Tutorial based on examples

Hi, I am looking for some good in depth tutorial on FPGA Editor. I have seen the video demos on youtube but they just g...
5 comments posted 18yrs
posted by sheikh.m.farhan
5 comments posted 18yrs posted by sheikh.m.farhan

Problem with PINs XC3S700A-4FG484

In the quick start tutorial, it says connect DIRECTION with PIN K13 (SW7 signal on board), but after browsing through u...
7 comments posted 18yrs
posted by fei.liu
7 comments posted 18yrs posted by fei.liu

Xilinx self-termination

Hi any info on ISE 10.1 ? maybe, HOPE really, Xilinx has done something to improve their software quality. It should be...
3 comments posted 18yrs
posted by Antti.Lukats
3 comments posted 18yrs posted by Antti.Lukats

Software Defined Radio on Xilinx Virtex 4

Hello, Let me right again in this forum on the same topic. But know in English. Whatever my English is very poor. I am...
2 comments posted 18yrs
posted by auguste.chindji
2 comments posted 18yrs posted by auguste.chindji

Interview questions

Hi I just came across some interview questions for digital design, and would like to discuss my solutions with you! #De...
22 comments posted 18yrs
posted by CBlank
22 comments posted 18yrs posted by CBlank

Software Defined Radio auf Xilinx Virtex 4

Hallo, ich arbeite seit 3 Monaten mit einem Xilinx Ml405 Virtex 4 Board und wollte darauf nun mal ein Software Defined...
9 comments posted 18yrs
posted by auguste.chindji
9 comments posted 18yrs posted by auguste.chindji

which IOSTANDARD to use for IO-bank in Spartan-3

Hi, We are currently designing a Xilinx Spartan-3 FPGA based tool that needs to communicate with a daughter card. Multi...
2 comments posted 18yrs
posted by tmpstrbox
2 comments posted 18yrs posted by tmpstrbox

Reconfiguration (on the fly) using SPARTAN 3A

Hi all, I want to know whether it is possible to program Spartan 3a for a run time partial reconfiguration. If yes are t...
20 comments posted 18yrs
posted by puneetjamrani
20 comments posted 18yrs posted by puneetjamrani

System generator hardware co-simulation interface

Hi, All! Need more info about system generator hardware co-simulation interface. Using JTAG for custom board very simpl...
0 comments posted 18yrs
posted by cuga.smonster
0 comments posted 18yrs posted by cuga.smonster