Field-Programmable Gate Arrays

FPGA Editor Tutorial based on examples

Hi, I am looking for some good in depth tutorial on FPGA Editor. I have seen the video demos on youtube but they just g...

5 comments posted 18yrs

posted by sheikh.m.farhan

5 comments posted 18yrs posted by sheikh.m.farhan

Xilinx DCM for frequency synthesis -- newbie question

I'm trying to use a DCM on a Spartan 3E to synthesize a frequency of 8 MHz but see only a constant 2 volts on the CLKFX...

17 comments posted 18yrs

posted by usenet

17 comments posted 18yrs posted by usenet

Problem with PINs XC3S700A-4FG484

In the quick start tutorial, it says connect DIRECTION with PIN K13 (SW7 signal on board), but after browsing through u...

7 comments posted 18yrs

posted by fei.liu

7 comments posted 18yrs posted by fei.liu

newbie seeking help to use xilinx spart-3a starter kit

Hello, I just received the package and it has the fpga board, usb cable, and power supply. I am am trying to it with Su...

2 comments posted 18yrs

posted by fei.liu

2 comments posted 18yrs posted by fei.liu

Actel FPGA programming using libero 8.1 generated SVF files

Hi Since version 8.1 Actel provides SVF programming file generation for A3 FPGA's but I have problems using those SVF f...

1 comments posted 18yrs

posted by Antti.Lukats

1 comments posted 18yrs posted by Antti.Lukats

Xilinx self-termination

Hi any info on ISE 10.1 ? maybe, HOPE really, Xilinx has done something to improve their software quality. It should be...

3 comments posted 18yrs

posted by Antti.Lukats

3 comments posted 18yrs posted by Antti.Lukats

Software Defined Radio on Xilinx Virtex 4

Hello, Let me right again in this forum on the same topic. But know in English. Whatever my English is very poor. I am...

2 comments posted 18yrs

posted by auguste.chindji

2 comments posted 18yrs posted by auguste.chindji

How to use xilinx specific features from Modelsim Designer 6.3a VHDL

Hi All, I have started a test design in Modelsim Designer. I now have one entity written in VHDL and have placed this e...

8 comments posted 18yrs

posted by stef33d

8 comments posted 18yrs posted by stef33d

Interview questions

Hi I just came across some interview questions for digital design, and would like to discuss my solutions with you! #De...

22 comments posted 18yrs

posted by CBlank

22 comments posted 18yrs posted by CBlank

Software Defined Radio auf Xilinx Virtex 4

Hallo, ich arbeite seit 3 Monaten mit einem Xilinx Ml405 Virtex 4 Board und wollte darauf nun mal ein Software Defined...

9 comments posted 18yrs

posted by auguste.chindji

9 comments posted 18yrs posted by auguste.chindji

which IOSTANDARD to use for IO-bank in Spartan-3

Hi, We are currently designing a Xilinx Spartan-3 FPGA based tool that needs to communicate with a daughter card. Multi...

2 comments posted 18yrs

posted by tmpstrbox

2 comments posted 18yrs posted by tmpstrbox

Reconfiguration (on the fly) using SPARTAN 3A

Hi all, I want to know whether it is possible to program Spartan 3a for a run time partial reconfiguration. If yes are t...

20 comments posted 18yrs

posted by puneetjamrani

20 comments posted 18yrs posted by puneetjamrani

System generator hardware co-simulation interface

Hi, All! Need more info about system generator hardware co-simulation interface. Using JTAG for custom board very simpl...

0 comments posted 18yrs

posted by cuga.smonster

0 comments posted 18yrs posted by cuga.smonster

ADPCM IP Core

Hi, For one of my projects, I am looking for ADPCM IP core. I found a previous thread and a Xilinx release note which s...

0 comments posted 18yrs

posted by togoli

0 comments posted 18yrs posted by togoli

V4FX: LVCMOS25 vs LVCMOS33 output buffer

Hi all, Is there a difference which one is instantiated when the actual VCC in the bank is 3.0V? Thanks, /Mikhail

9 comments posted 18yrs

posted by mbmsv

9 comments posted 18yrs posted by mbmsv