I'm looking for a "rule of thumb" of what I should expect in terms of jitter on the clock signal.
It should be relatively easy to find what jitter an oscillator has (e.g. one datasheet said 31ps peak-to-peak jitter (typical)). On the other hand, I have no idea what kind of jitter you could expect from effects that are caused by for example the PCB as I am not an expert on high speed PCB design.
Does anyone on this newsgroup either have any decent numbers or a good application note or similar resource they can point me to?
Ideally, I would like a rule of thumb like the following: "If the timing analyzer says your design can meet timing with a clock cycle of X ns, subtract Y ns from that to have a reasonable margin against clock jitter."
Is Y going to be in the ballpark of 0.05 ns, 0.5 ns, or even longer?
/Andreas