Field-Programmable Gate Arrays

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Chipscope 9.2 in XPS

Im trying to include a chipscope core into XPS 9.2 using the Debug configuration screen. When i set up the core and try...
0 comments posted 18yrs
posted by kislo02
0 comments posted 18yrs posted by kislo02

XST support for User Defined Primitives

Hi, Does anyone know if user defined Primitives are supported with XST, I have the following code and it is giving erro...
2 comments posted 18yrs
posted by togoli
2 comments posted 18yrs posted by togoli

HiTech Global Eval boards?

Hello I need a large Virtex-5 FPGA like the SX95T on a PCIe board with DDR2 memory. HiTech Global has a variety of boar...
1 comments posted 18yrs
posted by pdudley1
1 comments posted 18yrs posted by pdudley1

Question about Spartan 3E starter kit

Hi there - I'm very new to FPGAs and so I'm probably doing many dumb things. I recently got a Spartan 3E Starter Kit...
2 comments posted 18yrs
posted by nleahcim
2 comments posted 18yrs posted by nleahcim

Spartan3E startup problems

i got a problem with the Spartan 3E starter kit from Xilinx, no matter what Mode pins are set for, the DONE LED is alwa...
5 comments posted 18yrs
posted by kislo02
5 comments posted 18yrs posted by kislo02

simple example with timing problems

Hi, I wrote a simple stop watch for the Spartan 3 StarterKit. Unfortunately it seems to be unstable, i.e. sometimes whe...
3 comments posted 18yrs
posted by webmaster
3 comments posted 18yrs posted by webmaster

Need help on UNISIM.Vcomponents.all

Hi, I'm trying to port some code from Xilinx to Altera and I'm in a bit of a problem by not having UNISIM lib on Altera...
4 comments posted 18yrs
posted by cupidoREMOVE
4 comments posted 18yrs posted by cupidoREMOVE

Virtex4 FX PPC and Fsl

Hi, I have the following problem: I have designed a peripheral with a Fsl bus. It works fine when I create and EDK Proj...
1 comments posted 18yrs
posted by u_stadler
1 comments posted 18yrs posted by u_stadler

ISE 9.2 and Windriver

Hi, my Windriver trial period has expired, and then I found out that the license costs $900 ?!? Is it possible to bypas...
1 comments posted 18yrs
posted by webmaster
1 comments posted 18yrs posted by webmaster

case statements- verilog to vhdl

I have the following scenario in verilog which i need to convert to vhdl always if reset . . . else case . . . end case...
7 comments posted 18yrs
posted by FPGA.unknown
7 comments posted 18yrs posted by FPGA.unknown

64 bit WebPack

Will there be a 64 bit WebPack version of ISE in the near future? Rog.
9 comments posted 18yrs
posted by rogerwilson
9 comments posted 18yrs posted by rogerwilson

Xilinx tech Xclusive

What happend to the tech Xclusive articles that used to be on the Xilinx home page? I was trying to find one of Austins...
12 comments posted 18yrs
posted by noreply.larthe
12 comments posted 18yrs posted by noreply.larthe

Split register in smaller segments

Hi, I'm working on a little UART to get more familiar with verilog, and right now I have the following input: parameter...
5 comments posted 18yrs
posted by mickeymeeuw
5 comments posted 18yrs posted by mickeymeeuw