Latest threads in Field-Programmable Gate Arrays

Actel Cortex

Hey, Does anybody know if there is a port of Linux on the ARM-Cortex on Actel ? Thanks, John

1 18yrs

john

1 18yrs john

Which to learn: Verilog vs. VHDL?

Howdy - I'm just beginning with FPGAs. I am using a Spartan 3E Starter Kit with Xilinx ISE. I am an electrical engineer...

44 18yrs

nleahcim

44 18yrs nleahcim

Chipscope 9.2 in XPS

Im trying to include a chipscope core into XPS 9.2 using the Debug configuration screen. When i set up the core and try...

0 18yrs

kislo02

0 18yrs kislo02

XST support for User Defined Primitives

Hi, Does anyone know if user defined Primitives are supported with XST, I have the following code and it is giving erro...

2 18yrs

togoli

2 18yrs togoli

HiTech Global Eval boards?

Hello I need a large Virtex-5 FPGA like the SX95T on a PCIe board with DDR2 memory. HiTech Global has a variety of boar...

1 18yrs

pdudley1

1 18yrs pdudley1

Question about Spartan 3E starter kit

Hi there - I'm very new to FPGAs and so I'm probably doing many dumb things. I recently got a Spartan 3E Starter Kit...

2 18yrs

nleahcim

2 18yrs nleahcim

Spartan3E startup problems

i got a problem with the Spartan 3E starter kit from Xilinx, no matter what Mode pins are set for, the DONE LED is alwa...

5 18yrs

kislo02

5 18yrs kislo02

simple example with timing problems

Hi, I wrote a simple stop watch for the Spartan 3 StarterKit. Unfortunately it seems to be unstable, i.e. sometimes whe...

3 18yrs

webmaster

3 18yrs webmaster

Need help on UNISIM.Vcomponents.all

Hi, I'm trying to port some code from Xilinx to Altera and I'm in a bit of a problem by not having UNISIM lib on Altera...

4 18yrs

cupidoREMOVE

4 18yrs cupidoREMOVE

high noise/signal in a simple serial to mono dac module

Hello I am working on playing simple 11 kbytes/second 8bit WAV data through my FPGA stereo jack. I used the following s...

6 18yrs

fei.liu

6 18yrs fei.liu

Virtex4 FX PPC and Fsl

Hi, I have the following problem: I have designed a peripheral with a Fsl bus. It works fine when I create and EDK Proj...

1 18yrs

u_stadler

1 18yrs u_stadler

ISE 9.2 and Windriver

Hi, my Windriver trial period has expired, and then I found out that the license costs $900 ?!? Is it possible to bypas...

1 18yrs

webmaster

1 18yrs webmaster

case statements- verilog to vhdl

I have the following scenario in verilog which i need to convert to vhdl always if reset . . . else case . . . end case...

7 18yrs

FPGA.unknown

7 18yrs FPGA.unknown

64 bit WebPack

Will there be a 64 bit WebPack version of ISE in the near future? Rog.

9 18yrs

rogerwilson

9 18yrs rogerwilson

Xilinx tech Xclusive

What happend to the tech Xclusive articles that used to be on the Xilinx home page? I was trying to find one of Austins...

12 18yrs

noreply.larthe

12 18yrs noreply.larthe

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