Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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need recommendation for PCB fab & BGA assembly vendor, I'm in SF bay area
Hi. Does anyone have recommendations for a pcb fab vendor and an assembly vendor ? Preferably the same vendor but ok if not. This is for just a few small boards, 6-8 layers, a couple of FPGAs in bga...
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15 years ago
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FPGA Processor for Signal Processing ?
You find at the web and in books implementations of processors for FPGA =B4s and also processors like Picoblaze and Microblaze from firms like Xilinx. Are there also implementations of processors...
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15 years ago
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Using SRL16
Hello, I am trying to synthesize a simple 8-bit delay line (delay of 10) on Virtex2 xc2v40-4cs144 FPGA. My objective is to use LUT instead of available Flops inside each slice. After I synthesize I...
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15 years ago
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Aldec Active-HDL 7.3 sp1 [stimulators]
Hi all. I'm brand new in fpga subject so please be patient :P My problem is about to use stimulatorin waveform. Well, exactly- there is no such thing as stimulator as it was in ahdl 7.1. How to add it...
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15 years ago
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Forking in One-Hot FSMs
Having two bits hot in a one-hot FSM would normally be a bad thing. But I was wondering if anybody does this purposely, in order to fork, which might be a syntactically nicer way to have a concurrent...
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16 years ago
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quick question
I have written a VHDL code to generate random numbers using a "process". I want to implement the same using function/procedure so it be a part of a package. I would like to know if this should be done...
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16 years ago
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xilinx remote platform flash program
We are trying to develop a system that utilizes a Xilinx XC4VFX12 chip and platform flash. One of our main goals is to be able to remotely upgrade the bitfiles in the platform flash through ethernet...
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16 years ago
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Quartus v7.x fitting bug
Hello, Just trying this group as a bit of a last resort. I am currently working on a design that has identified a bug in Quartus v7.x (I have tried all versions up to 7.2sp3) on a Cyclone based...
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16 years ago
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Virtex4 Output Pins during Configuration
Hi all, I have a problem with a Virtex4 FPGA, I'm using it to control a motor ... but during the configuration output pins goes high and the motor moves. Is there any way to solve the problem without...
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16 years ago
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Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
I'm trying to get the .xsvf player in XAPP058 to work, but I haven't been able to do so. I have been able to do port.c, and I see signals that seem quite reasonable. But the FPGA DONE bit never gets...
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16 years ago
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Old FPGA question
Hi ! I have tried to enter the FPGA league for many years and I'm about to receive (at least ! the order was paid 6 months ago) my first prototype board with an Actel ProASIC. At last, I'll be able to...
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16 years ago
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ARM Cortex for Altera available
Hi looks like ARM is easing up Cortex licensing, so it is no only available for M1 enabled Actel but pretty much ALL FPGA vendors, available at the moment however seems to be only Altera Cyclone III...
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16 years ago
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NIOS II CFI interface
Hi,everybody,I am a fresher of NIOSII,and in the passed days ,I have been familar with the nios II system,also write some test program about the gpio,timer,uart and can work properly,today I add the...
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16 years ago
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co-sim for handel C with modelsim vs pure modelsim VHDL simulation
Hi, has anybody tried using co-sim for Handel C with modelsim? I managed to set up the co-sim environment, and got the handel C code to work with my EDK generated microblaze environment (in VHDL). In...
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16 years ago
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PCI Express Switch
Hi all, Wanted to verify a idea. Is is possible use Xilinx PCI express core in FPGA to use SMA ports for the physical layers rather than the normal PCI express slots? probably some parameters needs to...
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16 years ago
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