Field-Programmable Gate Arrays

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DSP48 Inference Template for XST

I'd like to infer a DSP48 in XST and can't find a template that will infer all of these opmodes: P=M P=M+C P=P+M P=P-M...
1 comments posted 18yrs
posted by kevin_neilson
1 comments posted 18yrs posted by kevin_neilson

NGC / EDIF Viewer

Suggestion: if you are using XST (or any other synthesis tool) and have Xilinx's PlanAhead, you can bring in an NGC/EDI...
0 comments posted 18yrs
posted by kevin_neilson
0 comments posted 18yrs posted by kevin_neilson

FPGA dev kit with 4-8 Cyclones or Spartans

Hello. We need a boards with 4 or 6 or even 8 identical FPGA chips installed, each one should be mid-range Altera Cyclo...
7 comments posted 18yrs
posted by climber.tim
7 comments posted 18yrs posted by climber.tim

Call VHDL module from Verilog

Hi, I have a basic question. Is is possible in the xilinx ISE enviroment to make a verilog wrapper of some VHDL code. I...
2 comments posted 18yrs
posted by rnunes
2 comments posted 18yrs posted by rnunes

Getting started with VHDL and Verilog

Hi all, My background is in Software Engineering C,C++,Java and Unix. I am getting started with VHDL and Verilog. What...
7 comments posted 18yrs
posted by jraj.thakkar
7 comments posted 18yrs posted by jraj.thakkar

warning from ISE 9.2

Hi, waht does that mean : Loading device for application Rf_Device from file '3s200.nph' in environment /home/thorsten/...
2 comments posted 18yrs
posted by webmaster
2 comments posted 18yrs posted by webmaster

BRAM initialization / bitstream configuration

Hi , The bitstream takes heed of BRAM , so my questions are : * Is it true that all the zeros that we localise in the b...
2 comments posted 18yrs
posted by bamboutcha9999
2 comments posted 18yrs posted by bamboutcha9999

How program PROM from msc file

---------- Forwarded message ---------- hello !! i have a problem with programming PROM , i must programing it in linux...
1 comments posted 18yrs
posted by zuzaila
1 comments posted 18yrs posted by zuzaila

Using Sysgen v8.2

Hello, I am trying to design a 4-tap FIR filter using system generator for Spartan3 xc3s200-4ft256. But when I try to g...
0 comments posted 18yrs
posted by partha.maji
0 comments posted 18yrs posted by partha.maji

Looking for FPGA/CPLD skills to develop prototype

I'm looking for an individual with FPGA/CPLD hardware and software skills to develop prototype of a consumer device. Chi...
0 comments posted 18yrs
posted by cjt101
0 comments posted 18yrs posted by cjt101

Silicon

Silicon Wafers at PCASilicon.com PCA supplies silicon wafers for the semiconductor industry. Our products include wafer...
0 comments posted 18yrs
posted by 854272335
0 comments posted 18yrs posted by 854272335

EDK9.2i simulation problems.

Hi 1) I am having some EDK simulation problems. I am using EDK9.2i with microblaze 7. I have attached a peripheral to t...
3 comments posted 18yrs
posted by chrisdekoh
3 comments posted 18yrs posted by chrisdekoh

FPGA Processor for Signal Processing ?

You find at the web and in books implementations of processors for FPGA =B4s and also processors like Picoblaze and Mic...
3 comments posted 18yrs
posted by HansWernerMarschke
3 comments posted 18yrs posted by HansWernerMarschke