OK, I thought I knew something and now I am confused by your answer.
A simulator will "execute" the VHDL and provide you with a verification (simulation) of whatever it is you are trying to do.
Targeting that VHDL to a synthesis tool will use a library of hardware elements (in an FPGA: LUTs, CLBs, etc; or in an ASIC: gates, registers, flip flops, etc) and result in a hardware design that performs the function you desired.
Some VHDL statements are for testing and test benches (simulation) and don't create hardware (like a "wait 5ns" statement), right?
The hardware only knows about clock edges, so every single element of the hardware (statement of VHDL) operates at once, there is no "sequence of operation" as there is in a c program, for example execute the first instruction, then the next, and so on -- does not exist in the synthesized hardware. In hardware it is on the next rising edge, do everything everywhere based on the last state of all of the registers, flip flops, latches, etc.