Latest threads in Field-Programmable Gate Arrays

Conversion from VERILOG READMEMB to INTEL HEX

Conversion from VERILOG READMEMB to INTEL HEX http://bknpk.no-ip.biz/readmemb_to_intel_hex/readmemb_to_intel_hex.html

0 18yrs

beky4kr

0 18yrs beky4kr

udp receive problem under nios

Hi ,everyone,now I use the NicheStack tcp/ip stack for sending and receiving the udp packets, the hardware platform is...

0 18yrs

bjzhangwn

0 18yrs bjzhangwn

ISE 9.2 - how do I extract component/slice placements for locking down a design?

Is there any NGD reader which can extract placement information? I know I can use FPGA editor and go through all the pri...

3 18yrs

fred__bloggs

3 18yrs fred__bloggs

Vritex2PRO: LVDCI for inputs?

Hi, I am using Virtex2Pro, and I have assigned LVDCI IO standards for all my LVCMOS receivers. I was wondering if LVDCI...

1 18yrs

togoli

1 18yrs togoli

Xilinx Platform USB Cable II

Hi I have intended an upgrade to Xilinx 9.2 or higher from version 7.1. With this newer versions my programming cable i...

3 18yrs

Clemens

3 18yrs Clemens

5 V oscillator output to GCLK

Hi, I am using a Spartan3 xc3s1000-4 fg456 FPGA. I have an oscillator which gives clk output at 5V p-p swing. I am usin...

24 18yrs

sheikh.m.farhan

24 18yrs sheikh.m.farhan

SDIO CRC7 + VCD waves

The SDIO standard defines two kinds of CRC. CRC7 for command and CRC16 for data. This code is a CRC7. The module is che...

1 18yrs

beky4kr

1 18yrs beky4kr

AHB and APB master VHDL generator

This project demonstrates an easy way to create AMBA masters and slaves. It includes an AHB master, AHB slave, APB maste...

1 18yrs

beky4kr

1 18yrs beky4kr

Anyway to secure a Xilinx NGC file ?

Hi, Is there anyway to secure a Xilinx NGC file from being reverse engineered ? Xilinx has a ngc2edif utility to conver...

6 18yrs

rats

6 18yrs rats

Spartan 3 Mapping Problem

So, I'm busily poking around at a Spartan 3 design, and can't get my latest iteration of things to build properly. I've...

5 18yrs

rgaddi

5 18yrs rgaddi

Virtex XCV1000E-6FG860C

Need help on a Virtex XCV1000E-6FG860C . I am short 500 pieces and the only parts I see are coming from China brokers....

5 18yrs

jon

5 18yrs jon

ML300 evaluation board broken?

Hi After two years I am back trying to use the ML300 evaluation platform for some FPGA programming. I connected the Mul...

0 18yrs

pg

0 18yrs pg

Quartus 7.2 and PCI Express

Good day! Have: -Quartus 7.2 SP3 -Megacore IP SP2 Need: -PCI Express. But I have only time_limited.sof In Quartus/tools...

9 18yrs

axalay

9 18yrs axalay

Dual rank DDR2 memory for Xilinx ML410 board

Hi, all, I am trying to make a PowerPC system with dual rank DDR2 on Xilinx ML410 board. When I set 2 banks and differe...

0 18yrs

yilu

0 18yrs yilu

EDK for spartan2?

Hi, We have a PC104 board with a spartan2 device. I tried to compile a microblaze system for this device but got the er...

2 18yrs

blop

2 18yrs blop

Field-Programmable Gate Arrays

Worth reading in Field-Programmable Gate Arrays