Field-Programmable Gate Arrays

ISE 9.2 - how do I extract component/slice placements for locking down a design?

Is there any NGD reader which can extract placement information? I know I can use FPGA editor and go through all the pri...

3 comments posted 18yrs

posted by fred__bloggs

3 comments posted 18yrs posted by fred__bloggs

Vritex2PRO: LVDCI for inputs?

Hi, I am using Virtex2Pro, and I have assigned LVDCI IO standards for all my LVCMOS receivers. I was wondering if LVDCI...

1 comments posted 18yrs

posted by togoli

1 comments posted 18yrs posted by togoli

Xilinx Platform USB Cable II

Hi I have intended an upgrade to Xilinx 9.2 or higher from version 7.1. With this newer versions my programming cable i...

3 comments posted 18yrs

posted by Clemens

3 comments posted 18yrs posted by Clemens

5 V oscillator output to GCLK

Hi, I am using a Spartan3 xc3s1000-4 fg456 FPGA. I have an oscillator which gives clk output at 5V p-p swing. I am usin...

24 comments posted 18yrs

posted by sheikh.m.farhan

24 comments posted 18yrs posted by sheikh.m.farhan

SDIO CRC7 + VCD waves

The SDIO standard defines two kinds of CRC. CRC7 for command and CRC16 for data. This code is a CRC7. The module is che...

1 comments posted 18yrs

posted by beky4kr

1 comments posted 18yrs posted by beky4kr

AHB and APB master VHDL generator

This project demonstrates an easy way to create AMBA masters and slaves. It includes an AHB master, AHB slave, APB maste...

1 comments posted 18yrs

posted by beky4kr

1 comments posted 18yrs posted by beky4kr

Anyway to secure a Xilinx NGC file ?

Hi, Is there anyway to secure a Xilinx NGC file from being reverse engineered ? Xilinx has a ngc2edif utility to conver...

6 comments posted 18yrs

posted by rats

6 comments posted 18yrs posted by rats

Spartan 3 Mapping Problem

So, I'm busily poking around at a Spartan 3 design, and can't get my latest iteration of things to build properly. I've...

5 comments posted 18yrs

posted by rgaddi

5 comments posted 18yrs posted by rgaddi

Virtex XCV1000E-6FG860C

Need help on a Virtex XCV1000E-6FG860C . I am short 500 pieces and the only parts I see are coming from China brokers....

5 comments posted 18yrs

posted by jon

5 comments posted 18yrs posted by jon

ML300 evaluation board broken?

Hi After two years I am back trying to use the ML300 evaluation platform for some FPGA programming. I connected the Mul...

0 comments posted 18yrs

posted by pg

0 comments posted 18yrs posted by pg

Quartus 7.2 and PCI Express

Good day! Have: -Quartus 7.2 SP3 -Megacore IP SP2 Need: -PCI Express. But I have only time_limited.sof In Quartus/tools...

9 comments posted 18yrs

posted by axalay

9 comments posted 18yrs posted by axalay

Dual rank DDR2 memory for Xilinx ML410 board

Hi, all, I am trying to make a PowerPC system with dual rank DDR2 on Xilinx ML410 board. When I set 2 banks and differe...

0 comments posted 18yrs

posted by yilu

0 comments posted 18yrs posted by yilu

EDK for spartan2?

Hi, We have a PC104 board with a spartan2 device. I tried to compile a microblaze system for this device but got the er...

2 comments posted 18yrs

posted by blop

2 comments posted 18yrs posted by blop

ps2 mouse protocol

Hi, I'm trying to communicate with the ps2 mouse. So I first force the ps2c line to '0' for 100us. Then I force the ps2...

2 comments posted 18yrs

posted by webmaster

2 comments posted 18yrs posted by webmaster

Does anyone have sdio protocol experience?

I am trying to write an sdio host controller. sdio is an extension to the sd/mmc protocol used on memory cards. It is u...

1 comments posted 18yrs

posted by alan

1 comments posted 18yrs posted by alan