Just trying this group as a bit of a last resort. I am currently working on a design that has identified a bug in Quartus v7.x (I have tried all versions up to 7.2sp3) on a Cyclone based design.
Naturally I was at first very skeptical that the bug was with Quartus, but after extensive use of signal probe I can see that a shift register is injecting spurious data. The design isn't particularly fast and is in one clock domain. What is very strange is that the back annotated simulation also exhibits the same bug - so I am sure the problem is with the fitting - not a signal integrity issue with our board. Looking at the technology map viewer, the LE elements appear to be as you would expect for a shift register.
We went through some time with mysupport, and Altera finally accepted that it was a bug. But since then dialog has broken down, we have heard basically nothing from them about a fix or when it might be available. Our distributor has also been in direct contact with the Altera UK & Ireland Channel Manager - but that has also been unsuccessful.
The support request was opened on the 14 Feb, and the last we heard any feedback was on the 18th March which is 2.5 months ago (seems pretty poor if you ask me).
I am not sure what avenue to try next, but hopefully there is someone reading this at Altera that could get in touch with the possibility of investigating this problem.
Kind regards, Ian Barnes.