Latest threads in Field-Programmable Gate Arrays

2-bit Pseudo Random Number Generator

Hi I should have some kind of PRNG that generates me for each clock 2 random bits. I was thinking for a start of implem...

9 18yrs

Clemens

9 18yrs Clemens

Problem with Scheduler in Xilkernel.

Hi. We are a couple of guys, working on a school project. We are trying to get the Xilkernel up and running, on the Spa...

4 18yrs

DonMadsen

4 18yrs DonMadsen

SKEW greater than Time period of CLK

could anybody please explain me ....whether is there any chance of clock skew being greater than or equal to the timepe...

2 18yrs

muralee.vkrishna

2 18yrs muralee.vkrishna

XILINX Ethernet MAC (URGENT...)

hello, I am trying to interface between my pc (windows) and a Xilinx Virtex2Pro board using ethernet. i am told i requi...

2 18yrs

vikram788

2 18yrs vikram788

XSA-50 implementation

Hello All, I have an XSA-50 board and am programming it to count the amount of high input signals from the header pins....

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uraniumore235

0 18yrs uraniumore235

Problem with conversions.vhd

I am using a vhdl conversion package from freemodelfoundry.com, conversions.vhd. The function I am having a problem wit...

7 18yrs

gnuarm

7 18yrs gnuarm

Xilinx ISE simulator

I am using the ISE simulator and I can't seem to figure out how to display variables in the waveform display. All of th...

0 18yrs

gnuarm

0 18yrs gnuarm

FPGA art

Hello everyone, Something quick to entertain you for a few minutes. I built an FPGA video synthesizer. You can see it i...

2 18yrs

checo22

2 18yrs checo22

System configuration for Xilinx ISE 10.1 - Virtex 5 LX110t or bigger FPGA

Hi, I have been running my designs on ISE 9.2i for a virtex-5 LX110t FPGA. The time taken by the tool to complete a ful...

2 18yrs

chethanzmail

2 18yrs chethanzmail

frame format virtex 5

hello , i v some questions about frame format in the bitstream of virtex 5 : * frame = 41 words = (41* 32) bits = 1312...

3 18yrs

swissiyoussef

3 18yrs swissiyoussef

agen Xilinx di Indonesia

PT Nesyer Electronic, agen resmi produk Xilinx dan bnayk merk semiconductor yang lain, www.nesyer.com, official represen...

0 18yrs

bmw318ie96

0 18yrs bmw318ie96

Vref IO problems with DDR SDRAM memory controller on a Virtex 4 LX25, ML401 board

Hi all, I'm trying to write a memory controller to make the use of DDR SDRAM possible. It's not going to be a high spee...

1 18yrs

mspiegels

1 18yrs mspiegels

What could be the problem?

========================================================================= * Design Hierarchy Analysis * ===============...

5 18yrs

pbantunez

5 18yrs pbantunez

Incorporating FPGAs on PCBs

Hi, I need to interconnect two or four FPGAs on a PCB, and I am looking at the prospect of designing these boards mysel...

17 18yrs

olson_ord

17 18yrs olson_ord

Length between blocks in FPGA

Hi to all, Is there a way for measuring the length -in terms of time of course- between the blocks in an FPGA? I am try...

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eneserdin

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