Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15253 Threads Posts
to

SKEW greater than Time period of CLK

could anybody please explain me ....whether is there any chance of clock skew being greater than or equal to the timepe...
2 comments posted 18yrs
posted by muralee.vkrishna
2 comments posted 18yrs posted by muralee.vkrishna

XILINX Ethernet MAC (URGENT...)

hello, I am trying to interface between my pc (windows) and a Xilinx Virtex2Pro board using ethernet. i am told i requi...
2 comments posted 18yrs
posted by vikram788
2 comments posted 18yrs posted by vikram788

XSA-50 implementation

Hello All, I have an XSA-50 board and am programming it to count the amount of high input signals from the header pins....
0 comments posted 18yrs
posted by uraniumore235
0 comments posted 18yrs posted by uraniumore235

Problem with conversions.vhd

I am using a vhdl conversion package from freemodelfoundry.com, conversions.vhd. The function I am having a problem wit...
7 comments posted 18yrs
posted by gnuarm
7 comments posted 18yrs posted by gnuarm

Xilinx ISE simulator

I am using the ISE simulator and I can't seem to figure out how to display variables in the waveform display. All of th...
0 comments posted 18yrs
posted by gnuarm
0 comments posted 18yrs posted by gnuarm

FPGA art

Hello everyone, Something quick to entertain you for a few minutes. I built an FPGA video synthesizer. You can see it i...
2 comments posted 18yrs
posted by checo22
2 comments posted 18yrs posted by checo22

frame format virtex 5

hello , i v some questions about frame format in the bitstream of virtex 5 : * frame = 41 words = (41* 32) bits = 1312...
3 comments posted 18yrs
posted by swissiyoussef
3 comments posted 18yrs posted by swissiyoussef

agen Xilinx di Indonesia

PT Nesyer Electronic, agen resmi produk Xilinx dan bnayk merk semiconductor yang lain, www.nesyer.com, official represen...
0 comments posted 18yrs
posted by bmw318ie96
0 comments posted 18yrs posted by bmw318ie96

What could be the problem?

========================================================================= * Design Hierarchy Analysis * ===============...
5 comments posted 18yrs
posted by pbantunez
5 comments posted 18yrs posted by pbantunez

Incorporating FPGAs on PCBs

Hi, I need to interconnect two or four FPGAs on a PCB, and I am looking at the prospect of designing these boards mysel...
17 comments posted 18yrs
posted by olson_ord
17 comments posted 18yrs posted by olson_ord

Length between blocks in FPGA

Hi to all, Is there a way for measuring the length -in terms of time of course- between the blocks in an FPGA? I am try...
1 comments posted 18yrs
posted by eneserdin
1 comments posted 18yrs posted by eneserdin

distributed RAM / BRAM

Hi , My question is silly but i need answers ! => what do we mean by saying " distributed RAM" inside FPGA ? what's the...
1 comments posted 18yrs
posted by bamboutcha9999
1 comments posted 18yrs posted by bamboutcha9999

LwBT port for microblaze

Dear all, may anybody help me to do the task. My task it to transmit some data over bluetooth from one FPGA to another...
0 comments posted 18yrs
posted by narendra.sisodiya
0 comments posted 18yrs posted by narendra.sisodiya