Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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distributed RAM / BRAM
Hi , My question is silly but i need answers ! => what do we mean by saying " distributed RAM" inside FPGA ? what's the difference between "bistributed RAM" and BRAM inside FPGA ? thank you
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15 years ago
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LwBT port for microblaze
Dear all, may anybody help me to do the task. My task it to transmit some data over bluetooth from one FPGA to another using Bluetooth link I have decided to use LwBT libraries which uses LwIP. but I...
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15 years ago
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difference between 8.2i and 9.2i with respect to Microblaze Core
We are using SPARTAN 3 E FPGA. I would like to know what is the difference between ISE 8.2i and ISE 9.2i with respect to the micro blaze core. We are able to access the FLASH and RTC via SPI in 8.2i...
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15 years ago
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Open source Core generators?
Dear All, Are there any Open source Core generators available? I am looking for FIR and FFT Core generators but also wonder if open source generators for other functions exist. Thanks in Advance
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15 years ago
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PCI to SATA of industrial class ( -40 - 85 )
Hi all, I need a SATA hard disk support through pci bus of my powerpc embedded system. After search a lot here and google, i think there is 4 ways: 1: use a PCI to SATA controller, but i can't find...
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15 years ago
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Altera Cyclone 3 external clamping diode
Hello, During implementation I get the following fitter warning: Warning: Following 1 pins must use external clamping diodes. Info: Pin Nios2Processor:_uP_MemInt_I2C:i_Nios2Processor|...
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15 years ago
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question about high speed serial links with clock forwarding in Virtex5 FPGAs
Hi, I have read several appnotes about serial interfaces in Xilinx FPGAs. Most of them use a DCM on the receiving side to phase shift and/or multiply the incoming clock. My problem is that I don't...
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15 years ago
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Camera link interface
Hello, I've implemented a camera link deserializer interface based on a virtex 4 FPGA (using ML402 development board). I'm using the LVDS 2.5 V inputs of the board and a cable with one end open. The...
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15 years ago
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Cyclone 3 on chip termination
Hi, I am drawing schematics for a new system that uses a Cyclone 3 FPGA. I have some LVTTL (3V3) signals on which I would like to use a 50R series termination. The Cyclone 3 has two possible 50R...
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15 years ago
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xilinx spi core question (microblaze)
anybody ever used the SPI core for microblaze? I found as example only a montevista spi driver which basically is doing all the bitbanging at a low level and uses it's own fifos, i.e. not using the...
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15 years ago
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FPGA imp
Hai, How to implement an FIR filter in FPGA...which approach is a good(linear convolution or circular convolution)which can be optimized area in FPGA... I am trying to follow the canonical structure...
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15 years ago
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How do I get Xilinx EDK to load a 'custom' XBD file?
When starting an EDK project, there is an option to download XBD files from the board vendor. After you have downloaded it (or written one), how do you get the EDK to use it? I've tried adding it to...
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15 years ago
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problem in using ICAP
Hi , I'm trying to partially reconfigure my device (XC2VP30 on XUP board) through ICAP. I have my ICAP attached to OPB which is attached to PowerPC. In bitgen.ut file I have set the value of mode pins...
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15 years ago
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demo board under 500usd
Hi everyone, I am considering to buy a fpga board for less than 500usd , I have looked around and I found 2 board that look like nice : the NIOS II development kit with a cycloneIII-25 that include a...
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15 years ago
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xilinx beginner modelsim question
Hi!!! I started recently with the xilinx software and these days I am trying to become more familiar with the modelsim and ise. I wanted to test some basic counter simulation in modelsim so I used...
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15 years ago
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