Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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2-bit Pseudo Random Number Generator
Hi I should have some kind of PRNG that generates me for each clock 2 random bits. I was thinking for a start of implementing an 8-bit LSFR and just using then the last two bits as output. I am just...
9
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15 years ago
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Problem with Scheduler in Xilkernel.
Hi. We are a couple of guys, working on a school project. We are trying to get the Xilkernel up and running, on the Spartan 3E starter kit. We are getting these streams from the debugger: XMK:...
4
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15 years ago
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SKEW greater than Time period of CLK
could anybody please explain me ....whether is there any chance of clock skew being greater than or equal to the timeperiod of the clock? If so,what are the effects? Any explaination would be deeply...
2
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15 years ago
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XILINX Ethernet MAC (URGENT...)
hello, I am trying to interface between my pc (windows) and a Xilinx Virtex2Pro board using ethernet. i am told i require Xilinx PLB Ethernet MAC ip core. i must admit i am very new to such work,...
2
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15 years ago
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2 | |
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XSA-50 implementation
Hello All, I have an XSA-50 board and am programming it to count the amount of high input signals from the header pins. The signal that I want to count is coming in at least 4ns as TTL signals--this...
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15 years ago
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Problem with conversions.vhd
I am using a vhdl conversion package from conversions.vhd. The function I am having a problem with is to_hex_str(slv,int). The simulation stops saying Value 3 is out of valid range : 1 TO 2 of subtype...
7
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15 years ago
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Xilinx ISE simulator
I am using the ISE simulator and I can't seem to figure out how to display variables in the waveform display. All of the documentation refers to "signals", but I am never sure if this term is used in...
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15 years ago
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FPGA art
Hello everyone, Something quick to entertain you for a few minutes. I built an FPGA video synthesizer. You can see it in action, plus some additional info here: (epileptics beware!) I have performed...
2
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15 years ago
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System configuration for Xilinx ISE 10.1 - Virtex 5 LX110t or bigger FPGA
Hi, I have been running my designs on ISE 9.2i for a virtex-5 LX110t FPGA. The time taken by the tool to complete a full synthesis and implementation is a little over 3 hours on a Core2 Quad CPU...
2
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15 years ago
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2 | |
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frame format virtex 5
hello , i v some questions about frame format in the bitstream of virtex 5 : * frame = 41 words = (41* 32) bits = 1312 bits , i would like to know the format of this frame ; i mean wich comes first...
3
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15 years ago
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agen Xilinx di Indonesia
PT Nesyer Electronic, agen resmi produk Xilinx dan bnayk merk semiconductor yang lain, official representative office of Avnet Inc, Xilinx authorized distributor
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15 years ago
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Vref IO problems with DDR SDRAM memory controller on a Virtex 4 LX25, ML401 board
Hi all, I'm trying to write a memory controller to make the use of DDR SDRAM possible. It's not going to be a high speed memory controller, but a basic...
1
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15 years ago
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What could be the problem?
========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy...
5
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15 years ago
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Incorporating FPGAs on PCBs
Hi, I need to interconnect two or four FPGAs on a PCB, and I am looking at the prospect of designing these boards myself. If any one has done this, I would be grateful if you could provide some...
17
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15 years ago
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Length between blocks in FPGA
Hi to all, Is there a way for measuring the length -in terms of time of course- between the blocks in an FPGA? I am trying to do this by using post- route simulations. I wonder if there is a much more...
1
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15 years ago
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