Field-Programmable Gate Arrays

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1250gbps input on virtex-5

Hi, we need to input a continous stream of 32 LVDS data bits at 1.25gbps per pin into a Virtex-5. There is a clock prov...
6 comments posted 18yrs
posted by ksulimma
6 comments posted 18yrs posted by ksulimma

problem with microblaze connected ip core

hi, Has anybody written ever an user_logic core for some device which is interfaced to a microblaze? I don't know what'...
1 comments posted 18yrs
posted by blop
1 comments posted 18yrs posted by blop

RS232 Interface

Hi I have an evaluation board with a target and a control FPGA. The control FPGA is connected to the target FPGA over 3...
3 comments posted 18yrs
posted by DanA
3 comments posted 18yrs posted by DanA

timing constraint is impossible to meet

Hi All, When compiling a design I receive the following message: :Pack:1653 - At least one timing constraint is impossi...
11 comments posted 18yrs
posted by wzab
11 comments posted 18yrs posted by wzab

Instantiating an lpm dcfifo in Verilog

Hello, I know many will say this is not an appropriate group to post such a question, but I wasn't getting any response...
1 comments posted 18yrs
posted by jjlindula
1 comments posted 18yrs posted by jjlindula

synthesis...

hai, I learned from the Xilinx manual that for,while do statements are synthesized in XST.. I would like to know how th...
7 comments posted 18yrs
posted by fazulu.vlsi
7 comments posted 18yrs posted by fazulu.vlsi

V4 - VTRX & AVCCAUXRX

Hi, DS302 - Pg 11, Table 12, Note 1 says "The maximum VTRX is 1.26V when bypassing the internal AC coupled VICM. VTRX m...
0 comments posted 18yrs
posted by mailtoakshat
0 comments posted 18yrs posted by mailtoakshat

bizarre state machine behavior

Hello, I ran into a bizarre state machine problem last week. I had a fairly simple state machine written in VHDL, with...
12 comments posted 18yrs
posted by elson
12 comments posted 18yrs posted by elson

HELP: a Funny asynchronous input design

input: Asynchronous, non-fix width, non-fix frequeny(but equal or smaller than 30 Mhz), something like random fast sign...
10 comments posted 18yrs
posted by aikenpang
10 comments posted 18yrs posted by aikenpang

Stratix IV Announced

Altera have put out a press release announcing Stratix IV. Handbook http://www.altera.com/literature/hb/stratix-iv/stx4...
16 comments posted 18yrs
posted by g1
16 comments posted 18yrs posted by g1

2-bit Pseudo Random Number Generator

Hi I should have some kind of PRNG that generates me for each clock 2 random bits. I was thinking for a start of implem...
9 comments posted 18yrs
posted by Clemens
9 comments posted 18yrs posted by Clemens

Problem with Scheduler in Xilkernel.

Hi. We are a couple of guys, working on a school project. We are trying to get the Xilkernel up and running, on the Spa...
4 comments posted 18yrs
posted by DonMadsen
4 comments posted 18yrs posted by DonMadsen