Latest threads in Field-Programmable Gate Arrays

distributed RAM / BRAM

Hi , My question is silly but i need answers ! => what do we mean by saying " distributed RAM" inside FPGA ? what's the...

1 18yrs

bamboutcha9999

1 18yrs bamboutcha9999

LwBT port for microblaze

Dear all, may anybody help me to do the task. My task it to transmit some data over bluetooth from one FPGA to another...

0 18yrs

narendra.sisodiya

0 18yrs narendra.sisodiya

difference between 8.2i and 9.2i with respect to Microblaze Core

We are using SPARTAN 3 E FPGA. I would like to know what is the difference between ISE 8.2i and ISE 9.2i with respect t...

3 18yrs

karthick.kr

3 18yrs karthick.kr

Open source Core generators?

Dear All, Are there any Open source Core generators available? I am looking for FIR and FFT Core generators but also won...

1 18yrs

kurtulmehtap

1 18yrs kurtulmehtap

PCI to SATA of industrial class ( -40 - 85 )

Hi all, I need a SATA hard disk support through pci bus of my powerpc embedded system. After search a lot here and goog...

1 18yrs

wicky.zhang

1 18yrs wicky.zhang

Altera Cyclone 3 external clamping diode

Hello, During implementation I get the following fitter warning: Warning: Following 1 pins must use external clamping d...

0 18yrs

Karel.Deprez

0 18yrs Karel.Deprez

question about high speed serial links with clock forwarding in Virtex5 FPGAs

Hi, I have read several appnotes about serial interfaces in Xilinx FPGAs. Most of them use a DCM on the receiving side...

1 18yrs

magne.munkejord

1 18yrs magne.munkejord

Camera link interface

Hello, I've implemented a camera link deserializer interface based on a virtex 4 FPGA (using ML402 development board)....

11 18yrs

Crhonos04

11 18yrs Crhonos04

Cyclone 3 on chip termination

Hi, I am drawing schematics for a new system that uses a Cyclone 3 FPGA. I have some LVTTL (3V3) signals on which I wou...

8 18yrs

Karel.Deprez

8 18yrs Karel.Deprez

xilinx spi core question (microblaze)

anybody ever used the SPI core for microblaze? I found as example only a montevista spi driver which basically is doing...

1 18yrs

blop

1 18yrs blop

FPGA imp

Hai, How to implement an FIR filter in FPGA...which approach is a good(linear convolution or circular convolution)which...

5 18yrs

fazulu.vlsi

5 18yrs fazulu.vlsi

How do I get Xilinx EDK to load a 'custom' XBD file?

When starting an EDK project, there is an option to download XBD files from the board vendor. After you have downloaded...

2 18yrs

ghelbig

2 18yrs ghelbig

problem in using ICAP

Hi , I'm trying to partially reconfigure my device (XC2VP30 on XUP board) through ICAP. I have my ICAP attached to OPB...

0 18yrs

fatma.abouelella

0 18yrs fatma.abouelella

demo board under 500usd

Hi everyone, I am considering to buy a fpga board for less than 500usd , I have looked around and I found 2 board that...

1 18yrs

alexis.gabin

1 18yrs alexis.gabin

xilinx beginner modelsim question

Hi!!! I started recently with the xilinx software and these days I am trying to become more familiar with the modelsim...

4 18yrs

Zorjak

4 18yrs Zorjak

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