Field-Programmable Gate Arrays

difference between 8.2i and 9.2i with respect to Microblaze Core

We are using SPARTAN 3 E FPGA. I would like to know what is the difference between ISE 8.2i and ISE 9.2i with respect t...

3 comments posted 18yrs

posted by karthick.kr

3 comments posted 18yrs posted by karthick.kr

Open source Core generators?

Dear All, Are there any Open source Core generators available? I am looking for FIR and FFT Core generators but also won...

1 comments posted 18yrs

posted by kurtulmehtap

1 comments posted 18yrs posted by kurtulmehtap

PCI to SATA of industrial class ( -40 - 85 )

Hi all, I need a SATA hard disk support through pci bus of my powerpc embedded system. After search a lot here and goog...

1 comments posted 18yrs

posted by wicky.zhang

1 comments posted 18yrs posted by wicky.zhang

Altera Cyclone 3 external clamping diode

Hello, During implementation I get the following fitter warning: Warning: Following 1 pins must use external clamping d...

0 comments posted 18yrs

posted by Karel.Deprez

0 comments posted 18yrs posted by Karel.Deprez

question about high speed serial links with clock forwarding in Virtex5 FPGAs

Hi, I have read several appnotes about serial interfaces in Xilinx FPGAs. Most of them use a DCM on the receiving side...

1 comments posted 18yrs

posted by magne.munkejord

1 comments posted 18yrs posted by magne.munkejord

Camera link interface

Hello, I've implemented a camera link deserializer interface based on a virtex 4 FPGA (using ML402 development board)....

11 comments posted 18yrs

posted by Crhonos04

11 comments posted 18yrs posted by Crhonos04

Cyclone 3 on chip termination

Hi, I am drawing schematics for a new system that uses a Cyclone 3 FPGA. I have some LVTTL (3V3) signals on which I wou...

8 comments posted 18yrs

posted by Karel.Deprez

8 comments posted 18yrs posted by Karel.Deprez

xilinx spi core question (microblaze)

anybody ever used the SPI core for microblaze? I found as example only a montevista spi driver which basically is doing...

1 comments posted 18yrs

posted by blop

1 comments posted 18yrs posted by blop

FPGA imp

Hai, How to implement an FIR filter in FPGA...which approach is a good(linear convolution or circular convolution)which...

5 comments posted 18yrs

posted by fazulu.vlsi

5 comments posted 18yrs posted by fazulu.vlsi

How do I get Xilinx EDK to load a 'custom' XBD file?

When starting an EDK project, there is an option to download XBD files from the board vendor. After you have downloaded...

2 comments posted 18yrs

posted by ghelbig

2 comments posted 18yrs posted by ghelbig

problem in using ICAP

Hi , I'm trying to partially reconfigure my device (XC2VP30 on XUP board) through ICAP. I have my ICAP attached to OPB...

0 comments posted 18yrs

posted by fatma.abouelella

0 comments posted 18yrs posted by fatma.abouelella

demo board under 500usd

Hi everyone, I am considering to buy a fpga board for less than 500usd , I have looked around and I found 2 board that...

1 comments posted 18yrs

posted by alexis.gabin

1 comments posted 18yrs posted by alexis.gabin

xilinx beginner modelsim question

Hi!!! I started recently with the xilinx software and these days I am trying to become more familiar with the modelsim...

4 comments posted 18yrs

posted by Zorjak

4 comments posted 18yrs posted by Zorjak

About the user defined instruction in APU

Hi, all, I am using ML410 board and EDK 8.2. I am trying to make a PPC system with APU support. I set the UID_1 registe...

0 comments posted 18yrs

posted by yilu

0 comments posted 18yrs posted by yilu

Yay! We're done with the quadrature encoder!

Aren't we? :-)

3 comments posted 18yrs

posted by newsgroup

3 comments posted 18yrs posted by newsgroup