Hi!!!
I started recently with the xilinx software and these days I am trying to become more familiar with the modelsim and ise. I wanted to test some basic counter simulation in modelsim so I used this simple code
counter design file
library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity counter is port( clk: in std_logic; reset: in std_logic; enable: in std_logic; count: out std_logic_vector(3 downto 0) ); end counter;
architecture behav of counter is signal pre_count: std_logic_vector(3 downto 0); begin process(clk, enable, reset) begin if reset = '1' then pre_count