Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Counter implementation with ise problem
Hi to everyone. I have some stupid problem that took lot of my time and if someone could help me please do so .I would be veryy greatfull I was implementing counter for my fpga (vhdl) and my code was...
7
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15 years ago
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Interrupt handler for Xilinx EMAC- URGENT!!
hello when i add a peripheral (plb EMAC in this case) from BSB to my embedded system (PPC405,ML300), do i have to explicitly write the drivers and, especially, an interrupt handler,and download them...
3
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15 years ago
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3 | |
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VHDL to Verilog Converter
Hi im looking for a vhdl to verilog converter. Im working with Trimode Ethernet MAC core which is written in VHDL. I have to modify this code but the problem is that I dont have any knowledge of VHDL....
3
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15 years ago
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3 | |
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using hard tri-mode ethernet MAC and MPMC on virtex 5
Hi, does anybody have any experience in using Virtex 5 FPGA with 1) MPMC 2) tr-mode ethernet MAC hard core with the xps_ll_temac and the ll_fifo? The card I am working on has an input of 100 MHz. this...
5
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15 years ago
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5 | |
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Checksums
hi all, Im working on a project in FPGAs called "network Traffic Manager" in verilog implemented in virtex 4. Im using trimode ethernet MAC core in it. Now i have to send a packet via ethernet to the...
4
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15 years ago
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4 | |
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Celoxica (AgilityDS) running on Gentoo
Hi, I am a lover of Gentoo, I managed to do almost everything including my life and work in Gentoo. The only one thing left stuck me is the Celoxica DK which is intended to be working at RHEL, SUSE,...
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15 years ago
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clock divider
How do I design a clock divider without using initial conditions. I designed once using initial values but they dont mean anything in synthesis. Thanks in advance for your help
1
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15 years ago
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1 | |
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Problem with Xilinx 9.2i and Modelsim 6.0
Hi, I`m trying to make a temporal simulation ( Post place & route model ) of a FPGA designed in Xilinx 9.2i in Modelsim 6.0, but the Modelsim gives me an error of type Error - (vsim 3193), refered...
1
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15 years ago
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1 | |
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Help with $setuphold
I am running a simulation after synthesis and I am getting the following error. ** Error: C:/Modeltech_xe_starter/library/lib18.v(9835): $hold( posedge CK &&& (flag == 1):54 ns, posedge E:54 ns, 500...
1
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15 years ago
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1 | |
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Combinatorial logic delay plus routing delay exceeds clock period
Generally speaking, it is not good, if a module's combinatoral logical delay plus the routing delay exceed the clock period. A certain module calculates a 100-bit accumulation in approxinately 5ns (in...
13
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15 years ago
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13 | |
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xilinx and jtag
I have a jtag programmer with a 20pin idc connector. Are these in general suitable for cplds/fpgas? Also, I have the following test program. The program is supposed to switch on a led when the input...
9
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15 years ago
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cutoff frequency
Hai, What is the cutoff frequency range setted for communication and multimedia application??And which is the optimal FIR filter design method suited for that?? regards, faz
15
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15 years ago
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15 | |
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Can I make ISE 9.2 ngdbuild stop generating new PERIOD specs on PLL outputs?
My Virtex5 design has a clock from an input pin going to a PLL that generates several clocks at different frequencies. My design treats these as asynchronous clocks, so I don't want the ISE timing...
4
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15 years ago
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DATA0 pin in Cyclone III device
Hi all, From the datasheet of 3c120 (cyclone III), the data[0] is a pin used in configuration, and in user mode it can be used as a dedicated input pin with "optional user control". But when I use it...
1
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15 years ago
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1 | |
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dual port ramb16 problem
Hi, In my transciever design I am using ramb16_s18_s36 blocks for both receiver and transmitter. In the synthesis report ISE says something about these rams that some pins are unconnected etc. but...
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15 years ago
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