Field-Programmable Gate Arrays

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Spartan3 interface with DDR SDRAM

I would like some suggestions on interfacing the Xilinx Spartan3 device with a DDR SDRAM. The idea is to build a contro...
2 comments posted 18yrs
posted by FPGA.unknown
2 comments posted 18yrs posted by FPGA.unknown

Anyone used HiTech global boards?

Hello, I have been using Xilinx MLxxx series boards. For the first time, we are planning to buy a PCIe evaluation board...
0 comments posted 18yrs
posted by muthusnv
0 comments posted 18yrs posted by muthusnv

FPGA clock frequency

Hai, I am pretty clear about cutoff and sampling frequency of FIR filter. Wat r all the FIR filter constraints to be co...
36 comments posted 18yrs
posted by fazulu.vlsi
36 comments posted 18yrs posted by fazulu.vlsi

UART master core

Hello, I have 2 boards, of which one has PPC core and other do not. [board1 /w PPC]-------uart-------[board2 /wo PPC] I...
1 comments posted 18yrs
posted by muthusnv
1 comments posted 18yrs posted by muthusnv

EAPR and EDK 9.1.02i

Hello, In the version of partial reconfiguration tools for ISE 9.1i SP2, Xilinx released several reference designs usin...
0 comments posted 18yrs
posted by leumig78
0 comments posted 18yrs posted by leumig78

Xilinx cuts 250 jobs.

http://www.edn.com/article/CA6566989.html
31 comments posted 18yrs
posted by symon_brewer
31 comments posted 18yrs posted by symon_brewer

Xilinx vs Altera

Sorry about the title, everyone put down the flamethrowers, lol. I have a few questions about Xilinx and Altera (actual...
23 comments posted 18yrs
posted by lists
23 comments posted 18yrs posted by lists

Xilinx Fifo Generator Direct Instantiation?

Does anybody know if it is possible to directly instantiate a Xilinx Fifo Generator asynchronous fifo in VHDL? I have a...
3 comments posted 18yrs
posted by paragon.john
3 comments posted 18yrs posted by paragon.john

Using ethernet on a Xilnx board (Help appreciated)

First of all let me apologize for any thing of things I"m ignorant about here. Up until very recenty my programming exp...
10 comments posted 18yrs
posted by AchatesAVC
10 comments posted 18yrs posted by AchatesAVC

puzzling [and deceiving ?] Actel kit

Hello, I'm sorry for this post but I don't want to rant for nothing, being the optimistic guy that some people know......
2 comments posted 18yrs
posted by whygee
2 comments posted 18yrs posted by whygee

ANNC: ISE WebPACK 10.1i tutorial available

For those that are just getting started with using Xilinx FPGAs, we have released a new version of our ISE/WebPACK tuto...
0 comments posted 18yrs
posted by devb
0 comments posted 18yrs posted by devb

Counter implementation with ise problem

Hi to everyone. I have some stupid problem that took lot of my time and if someone could help me please do so .I would...
7 comments posted 18yrs
posted by Zorjak
7 comments posted 18yrs posted by Zorjak

Interrupt handler for Xilinx EMAC- URGENT!!

hello when i add a peripheral (plb EMAC in this case) from BSB to my embedded system (PPC405,ML300), do i have to expli...
3 comments posted 18yrs
posted by vikram788
3 comments posted 18yrs posted by vikram788