Latest threads in Field-Programmable Gate Arrays

HDL tricks for better timing closure in FPGAs

Hi, I am working with FPGAs and trying to take advantage of the parallelism that is available in them. My design is in...

13 18yrs

jaydev.shelat

13 18yrs jaydev.shelat

Your favourite DSP textbooks/websites?

hi folks You may have noticed that I've been struggling to explain some rather basic stuff about FIR filters to someone...

7 18yrs

jonathan.bromley

7 18yrs jonathan.bromley

Spartan3 interface with DDR SDRAM

I would like some suggestions on interfacing the Xilinx Spartan3 device with a DDR SDRAM. The idea is to build a contro...

2 18yrs

FPGA.unknown

2 18yrs FPGA.unknown

Anyone used HiTech global boards?

Hello, I have been using Xilinx MLxxx series boards. For the first time, we are planning to buy a PCIe evaluation board...

0 18yrs

muthusnv

0 18yrs muthusnv

FPGA clock frequency

Hai, I am pretty clear about cutoff and sampling frequency of FIR filter. Wat r all the FIR filter constraints to be co...

36 18yrs

fazulu.vlsi

36 18yrs fazulu.vlsi

UART master core

Hello, I have 2 boards, of which one has PPC core and other do not. [board1 /w PPC]-------uart-------[board2 /wo PPC] I...

1 18yrs

muthusnv

1 18yrs muthusnv

A new FPGA company comes out of Stealth mode - SiliconBlue

Seems there is room for one more ? http://www.siliconbluetech.com/news.html This seems to push the low-power envelope a...

12 18yrs

no.spam

12 18yrs no.spam

EAPR and EDK 9.1.02i

Hello, In the version of partial reconfiguration tools for ISE 9.1i SP2, Xilinx released several reference designs usin...

0 18yrs

leumig78

0 18yrs leumig78

Xilinx cuts 250 jobs.

http://www.edn.com/article/CA6566989.html

31 18yrs

symon_brewer

31 18yrs symon_brewer

Compare and update in same clock cycle synthesis problem

Something simular to the following code fragments works in pre-synthesis simulation, but not in real hardware and post...

7 18yrs

stef33d

7 18yrs stef33d

Xilinx vs Altera

Sorry about the title, everyone put down the flamethrowers, lol. I have a few questions about Xilinx and Altera (actual...

23 18yrs

lists

23 18yrs lists

Xilinx Fifo Generator Direct Instantiation?

Does anybody know if it is possible to directly instantiate a Xilinx Fifo Generator asynchronous fifo in VHDL? I have a...

3 18yrs

paragon.john

3 18yrs paragon.john

Using ethernet on a Xilnx board (Help appreciated)

First of all let me apologize for any thing of things I"m ignorant about here. Up until very recenty my programming exp...

10 18yrs

AchatesAVC

10 18yrs AchatesAVC

puzzling [and deceiving ?] Actel kit

Hello, I'm sorry for this post but I don't want to rant for nothing, being the optimistic guy that some people know......

2 18yrs

whygee

2 18yrs whygee

ANNC: ISE WebPACK 10.1i tutorial available

For those that are just getting started with using Xilinx FPGAs, we have released a new version of our ISE/WebPACK tuto...

0 18yrs

devb

0 18yrs devb

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