Field-Programmable Gate Arrays

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VHDL to Verilog Converter

Hi im looking for a vhdl to verilog converter. Im working with Trimode Ethernet MAC core which is written in VHDL. I ha...
3 comments posted 18yrs
posted by amboafridi
3 comments posted 18yrs posted by amboafridi

Checksums

hi all, Im working on a project in FPGAs called "network Traffic Manager" in verilog implemented in virtex 4. Im using...
4 comments posted 18yrs
posted by amboafridi
4 comments posted 18yrs posted by amboafridi

Celoxica (AgilityDS) running on Gentoo

Hi, I am a lover of Gentoo, I managed to do almost everything including my life and work in Gentoo. The only one thing...
0 comments posted 18yrs
posted by wlpstxzhd
0 comments posted 18yrs posted by wlpstxzhd

clock divider

How do I design a clock divider without using initial conditions. I designed once using initial values but they dont mea...
1 comments posted 18yrs
posted by FPGA.unknown
1 comments posted 18yrs posted by FPGA.unknown

Problem with Xilinx 9.2i and Modelsim 6.0

Hi, I`m trying to make a temporal simulation ( Post place & route model ) of a FPGA designed in Xilinx 9.2i in Modelsim...
1 comments posted 18yrs
posted by ghuardian
1 comments posted 18yrs posted by ghuardian

Help with $setuphold

I am running a simulation after synthesis and I am getting the following error. ** Error: C:/Modeltech_xe_starter/libra...
1 comments posted 18yrs
posted by FPGA.unknown
1 comments posted 18yrs posted by FPGA.unknown

xilinx and jtag

I have a jtag programmer with a 20pin idc connector. Are these in general suitable for cplds/fpgas? Also, I have the fo...
9 comments posted 18yrs
posted by <discussions
9 comments posted 18yrs posted by <discussions

cutoff frequency

Hai, What is the cutoff frequency range setted for communication and multimedia application??And which is the optimal FI...
15 comments posted 18yrs
posted by fazulu.vlsi
15 comments posted 18yrs posted by fazulu.vlsi

DATA0 pin in Cyclone III device

Hi all, From the datasheet of 3c120 (cyclone III), the data[0] is a pin used in configuration, and in user mode it can...
1 comments posted 18yrs
posted by Tommy.Ai
1 comments posted 18yrs posted by Tommy.Ai

dual port ramb16 problem

Hi, In my transciever design I am using ramb16_s18_s36 blocks for both receiver and transmitter. In the synthesis repor...
0 comments posted 18yrs
posted by eneserdin
0 comments posted 18yrs posted by eneserdin

FIR in FPGA

Hai, 1.Can i set the clock frequency of the FIR filter at any frequency i want... but pretty much higher than the sampl...
3 comments posted 18yrs
posted by fazulu.vlsi
3 comments posted 18yrs posted by fazulu.vlsi

RGB video panel

Hi everyone,i am trying to display a video on a rgb leds.The leds would be connected to the fpga what i was concerned a...
1 comments posted 18yrs
posted by ankitanand1986
1 comments posted 18yrs posted by ankitanand1986