Latest threads in Field-Programmable Gate Arrays

Counter implementation with ise problem

Hi to everyone. I have some stupid problem that took lot of my time and if someone could help me please do so .I would...

7 18yrs

Zorjak

7 18yrs Zorjak

Interrupt handler for Xilinx EMAC- URGENT!!

hello when i add a peripheral (plb EMAC in this case) from BSB to my embedded system (PPC405,ML300), do i have to expli...

3 18yrs

vikram788

3 18yrs vikram788

VHDL to Verilog Converter

Hi im looking for a vhdl to verilog converter. Im working with Trimode Ethernet MAC core which is written in VHDL. I ha...

3 18yrs

amboafridi

3 18yrs amboafridi

using hard tri-mode ethernet MAC and MPMC on virtex 5

Hi, does anybody have any experience in using Virtex 5 FPGA with 1) MPMC 2) tr-mode ethernet MAC hard core with the xps...

5 18yrs

chrisdekoh

5 18yrs chrisdekoh

Checksums

hi all, Im working on a project in FPGAs called "network Traffic Manager" in verilog implemented in virtex 4. Im using...

4 18yrs

amboafridi

4 18yrs amboafridi

Celoxica (AgilityDS) running on Gentoo

Hi, I am a lover of Gentoo, I managed to do almost everything including my life and work in Gentoo. The only one thing...

0 18yrs

wlpstxzhd

0 18yrs wlpstxzhd

clock divider

How do I design a clock divider without using initial conditions. I designed once using initial values but they dont mea...

1 18yrs

FPGA.unknown

1 18yrs FPGA.unknown

Problem with Xilinx 9.2i and Modelsim 6.0

Hi, I`m trying to make a temporal simulation ( Post place & route model ) of a FPGA designed in Xilinx 9.2i in Modelsim...

1 18yrs

ghuardian

1 18yrs ghuardian

Help with $setuphold

I am running a simulation after synthesis and I am getting the following error. ** Error: C:/Modeltech_xe_starter/libra...

1 18yrs

FPGA.unknown

1 18yrs FPGA.unknown

Combinatorial logic delay plus routing delay exceeds clock period

Generally speaking, it is not good, if a module's combinatoral logical delay plus the routing delay exceed the clock pe...

13 18yrs

no-reply

13 18yrs no-reply

xilinx and jtag

I have a jtag programmer with a 20pin idc connector. Are these in general suitable for cplds/fpgas? Also, I have the fo...

9 18yrs

<discussions

9 18yrs <discussions

cutoff frequency

Hai, What is the cutoff frequency range setted for communication and multimedia application??And which is the optimal FI...

15 18yrs

fazulu.vlsi

15 18yrs fazulu.vlsi

Can I make ISE 9.2 ngdbuild stop generating new PERIOD specs on PLL outputs?

My Virtex5 design has a clock from an input pin going to a PLL that generates several clocks at different frequencies....

4 18yrs

barry374

4 18yrs barry374

DATA0 pin in Cyclone III device

Hi all, From the datasheet of 3c120 (cyclone III), the data[0] is a pin used in configuration, and in user mode it can...

1 18yrs

Tommy.Ai

1 18yrs Tommy.Ai

dual port ramb16 problem

Hi, In my transciever design I am using ramb16_s18_s36 blocks for both receiver and transmitter. In the synthesis repor...

0 18yrs

eneserdin

0 18yrs eneserdin

Field-Programmable Gate Arrays

Worth reading in Field-Programmable Gate Arrays