Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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FIR in FPGA
Hai, 1.Can i set the clock frequency of the FIR filter at any frequency i want... but pretty much higher than the sample rate? for example :Fc=3.5khz Fs=8khz can i clock as any value >8khz say...
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15 years ago
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RGB video panel
Hi everyone,i am trying to display a video on a rgb leds would be connected to the fpga what i was concerned about is that which video format can be displayed easily on the leds..Waiting for your...
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15 years ago
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Xilinx Clock Doubler
I have a 10MHz clock but needed a 20MHz clock speed. I used two asynchronous clear flip flops with a series of buffers to add delay to the signal. Is this a bad practice? Will it fail with time or...
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15 years ago
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Are FPGAs headed toward a coarse granularity?
I was reading about the MathStar FPOA devices and I started thinking about parallels between the architectural advances in CPUs compared to FPGAs. With the increases in speed with process refinements...
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15 years ago
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FIFO verses RAMB
In the Xilinx Virtex 4 architecture, does anyone know when you instantiate a FIFO using the FIFO16 blocks does the FIFO use the RAMB16 block next to it for its memory, or does the FIFO16 has its own...
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15 years ago
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HDL - simulation vs synthesis
I run Xilinx ISE v10.1 and use VHDL. I have put together a fairly small circuit that merely sends out solid colors and sync signals on a VGA line. During the active video portion of time, a color...
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15 years ago
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Virtex 2 with PLB_v34 and EDK 10.1
Hi, I'm trying to build a system for a XC2V6000 FPGA. The problem I have is that I have to implement a PLB. But the PLB shipped with the EDK 10.1 is the PLB_v46 which doesn't support the virtex II,...
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15 years ago
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error when 'generating simulation hdl files' in xilinx xps
hi, does anyone know how to solve this error when selecting 'generate simulation hdl files' in xps (xilinx edk 9.1): ------------------------------------------------------------------ ... Analyzing...
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15 years ago
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Sequentially syncrhronous
Sorry, Guys. We're not quite done yet with the quadrature encoder. I tried to rewrite it as a synchronous process. The behavioral sim shows it working as intended. The post-route sim and onboard test...
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15 years ago
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JTAG + PROM error!
Hi, I have the problem that I can't communicate with my Xilinx XCF04S PROM through JTAG. The circuit setup is a "3.3V Master-Serial Configuration with 3.3V and JTAG with Platform Flash Prom" as here:...
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15 years ago
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Need comparison table about Xilinx ISE WebPack 10.1i vs ISE Foundation 10.1i
Does anyone have comparison table about Xilinx ISE WebPack 10.1i vs ISE Foundation 10.1i ? Because I was confused by their license and available features. Thank you.
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15 years ago
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Mathstar plans to discontinue FPOA development
News: "As it seeks a buyer, MathStar said it plans to discontinue its field programmable object array (FPOA) chip development and its board-level systems development businesses." Did they ever get to...
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15 years ago
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HWICAP initialization
hi all, I am trying to use HWICAP to configure certain LUTs , I guess that starting with the examples from XILINX will be a good start, the problem that after many trials and of course nothing...
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15 years ago
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FIR filter o/p width
Hai, Is there any formula or general rule to set output width of FIR filter given its input ,coefficients width and number of taps.?? I red in some data sheet of FIR filter deisgn as: output width =...
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15 years ago
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Ph.D Student
Good morning. I am currently seeking any publication of my work with FPGA devices, especially for obtaining Ph.D Student. Specifically I've introduced a middleware of communications for FPGA...
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15 years ago
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