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Counter implementation with ise problem

Hi to everyone. I have some stupid problem that took lot of my time and if someone could help me please do so .I would be veryy greatfull

I was implementing counter for my fpga (vhdl)

and my code was thi

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity counter is generic ( width: positive:=8); port ( CE: in std_logic; C: in std_logic; CLR: in std_logic; RST: in std_logic; Q: out std_logic_vector(width-1 downto 0); CEO: out std_logic; TC: out std_logic); end counter;

architecture Behavioral of counter is

constant TERMINAL_COUNT: std_logic_vector (width-1 downto 0) := (others=>'1'); signal Q_internal: std_logic_vector (width-1 downto 0); signal TC_internal: std_logic;

begin

process (CLR, C, CE, RST) begin if CLR = '1' then Q_internal '0'); elsif C'event and C='1' then if RST

Reply to
Zorjak
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Check what you've done with the counter's OUTPUTS. If they don't find their way to a device output pin, then the whole counter will ultimately be optimised away, leaving its input signals unused.

Oh - and while you're checking, remove CE and RST from the sensitivity list of your clocked logic. They're synchronous controls, and shouldn't trigger the clocked process. In VHDL it does no harm except to confuse the reader and waste simulation time, but if you did the same thing in Verilog you would get crazy behaviour in simulation.

Also, when you have some leisure time, trawl the recent archives of comp.lang.vhdl for discussions on NUMERIC_STD, to understand why many of us don't much like your code :-)

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Jonathan Bromley, Consultant

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Reply to
Jonathan Bromley

Hi Zoran, wasn't there something in your synthesis report telling you that Q_internal (or Q) will be tied to a constant value?

Have a look at your code where you wrote

if RST if RST Q_internal '0');

Have a nice synthesis Eilert

Reply to
backhus

Thank you very much for the help.

Yes you were right. My code wasn't good. The stupid mistake in code. I can't believe what I've wrote. But you must admit that warring that I was getting from ISE were totally unasociative. That confused me totally. :):)

Thank you one more time for all your help Zoran

Reply to
Zorjak

Reply to
Jonathan Bromley

A synthesis tool's job is to turn code into an implementation, it makes no assumptions about whether what you've written functions as you intended. A simulator's job is to model the functionality of the code and help you to find design errors in your code, the simulator couldn't care less about whether what you've written can be synthesized.

When you use the wrong tool, don't complain about the results. Using both somewhat together can be useful, the preliminary synthesis results pointing to possible logical design errors.

KJ

Reply to
KJ

Hi Zoran, when there's a problem with code semantic, warnings are just indirect hints. Just before the sections where the warnings are generated you can read this:

=========================================================================

  • HDL Analysis * ========================================================================= Analyzing generic Entity in library (Architecture ). width = 8 INFO:Xst:2679 - Register in unit has a constant value of 00000000 during circuit operation. The register is replaced by logic. Entity analyzed. Unit generated.

And the info tells you, that there is no counter anymore since the counter register has been replaced by a constant value. And at that point all alarms should ring that something went terribly wrong. (Unless you know what you did, and did it for a purpose.)

So, even when you get no errors and warnings at all, always have a look at the infos and other messages in the synthesis report.

Besides, a simulation should have shown you that your counter isn't working anyway.

Have a nice synthesis Eilert

Reply to
backhus

Thanks for those tips Eliert. I've do sinthesis and impelmentation together and I knew that my counter isn't implemetned because nothing was ocupied. THe thing is that I started with Xilinx a while ago and i have just a little experience with Quartus form college. There if something like this happenes quartus would give me the warning that my Q has constant value. Somethng like this info you said me to read but there it would be warning. I think that this would be better but important is that I solve this problem and that I've learned something new. I'll get used on xilinx soon, I hope:)

Thanks one more time for your help Zoran

Reply to
Zorjak

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