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using hard tri-mode ethernet MAC and MPMC on virtex 5

Hi, does anybody have any experience in using Virtex 5 FPGA with

1) MPMC 2) tr-mode ethernet MAC hard core with the xps_ll_temac and the ll_fifo?

The card I am working on has an input of 100 MHz. this is the problem that I face, something which i am not sure:

1) MPMC has to run at a multiple of 133 MHz etc...thus the whole microblaze PLB system has to run at 133 MHz? 2) the xps_ll_temac requires some clocks like MGTCLK and GTX_CLK_0 at 125 MHz and 200 MHz respectively. Can these clocks required by the TEMAC be generated off the clock generator such that they are not running at same frequency as the system clock (ie the PLB bus clock SPB_Clk).

does anyone have any idea?

thanks! Chris

Reply to
chrisdekoh
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When you generate the core, please select clock generate. so you only need to give only one clock into the TEMAC then it will use DCM to generate what it need

Reply to
Aiken

MPMC and PLB can run at different frequencies. I don't think there is a need for a relation between them atleast from what I have read from the docs. Also are you using a GTP/GTX , then you need a 200Mhz clock for the GTP's and 125Mhz for the PHY. If not I am not sure why do you need a 200Mhz clock for the TEMAC...

Also the other question I have is by a "clock generator", do you mean an external clock generator or just an clock generator IC. If you can provide more info, then probably I can help you out. You can also look at reference designs from Xilinx for ML505/ML506.

--parag

Reply to
beeraka

Hi Parag, Aiken, thanks for your inputs. They are very helpful.

Hi Parag, when i mean clock generator, i mean the EDK clock generator module which generates clocks on board the FPGA using DCMs, deriving clocks based on what the user wants. will look at ML505 and ML506 reference designs.

thanks again Chris

Reply to
chrisdekoh

Are you using the 88E111 Marvell PHY by any chance because I remember seeing GTX_CLK etc.. Anyways GTX_CLK and RX_CLK on the PHY are inputs to the FPGA .But you need XTAL for the PHY. You can look at the EDK reference design for ML505 too...

--parag

Reply to
beeraka

It's not documented, but you can drive the ll_temac MGT_CLKP from an internally derived DCM clock (external differential clock not required).

However, there is a special magical XIL_... setting that you need to get through DRC.

export XIL_MAP_NO_GT_CLKIN_DRC=1

Hope this helps,

John

Reply to
John Williams

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