Field-Programmable Gate Arrays

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SDRAM controller

I am looking for a SDRAM controller for Xilinx Spartan3 device in Verilog. xapp 134 has one which targets virtex 2 devi...
4 comments posted 18yrs
posted by FPGA.unknown
4 comments posted 18yrs posted by FPGA.unknown

TI DSP + Virtex-5 using EMIF interface

Hi all, I'm working on a realtime application that requires to elaborate a digital video stream 25fps. Algorithms are v...
2 comments posted 18yrs
posted by giuliopulina
2 comments posted 18yrs posted by giuliopulina

FPGA reprogrammable? (urgent)

hello.... i wanted to know if fpgas were reprogrammable... if i have a virtex2pro board, use it for a system, and later...
3 comments posted 18yrs
posted by vikram788
3 comments posted 18yrs posted by vikram788

Deskew Clock on Synchronous Bus

I am having difficulties in trying to deskew the Clock on a synchronous local bus interface between a Virtex4 FPGA and...
4 comments posted 18yrs
posted by bill.ngo
4 comments posted 18yrs posted by bill.ngo

ANNOUNCE: TimingAnalyzer -- new updated version

Hello All, A new version beta 0.83 is now available. The following changes and additions have occurred. * Improved Imag...
3 comments posted 18yrs
posted by timinganalyzer
3 comments posted 18yrs posted by timinganalyzer

Nastat vs.kitkat tuore tutkimus

Transmutaatiotekniikasta. *Maassamme ydinalalla on tuskin mitään niin tarkoin TABU:na pirettyä systeemiä, kuin mahdolli...
0 comments posted 18yrs
posted by artturi
0 comments posted 18yrs posted by artturi

Nutritional yeast

Yksinkertainen kysymys: "Mitä Suomen valtion kansantalous saa tehtyä niillä 100% puhtailla energiamäärillään, joita sil...
0 comments posted 18yrs
posted by severi
0 comments posted 18yrs posted by severi

NIOS-II+LAN91C111

Hi,everyone,I am now doing a work about ALTERA nios-II.The FPGA I use is cycII-60,and the cpu is NIOS-II f,sdram ,lan91...
3 comments posted 18yrs
posted by bjzhangwn
3 comments posted 18yrs posted by bjzhangwn

Extracting market feedback from Usenet traffic

I have monitored this group for a while and written a thesis about the possibility to extract market feedback from Usen...
0 comments posted 18yrs
posted by fbertram
0 comments posted 18yrs posted by fbertram

Re: 1 Pin MTE Cable

"HT-Lab" schrieb im Newsbeitrag news:DTd2k.59$ snipped-for-privacy@newsfe05.ams... > Hi all, > > Does anybody know a go...
0 comments posted 18yrs
posted by techseller
0 comments posted 18yrs posted by techseller

FPGA to FLASH and back?

Hi, I'd like to use an Intel StrataFlash Memory 28F320J3A with my Virtex4 FPGA and write / read data from it. Is there...
3 comments posted 18yrs
posted by denkedranjoe
3 comments posted 18yrs posted by denkedranjoe

length compensation for RocketIO channels

Hi there, I'm designing a PCB that incorporates a Virtex4 FX60 with 16 RocketIOs. All RocketIOs function only as a rece...
1 comments posted 18yrs
posted by denkedranjoe
1 comments posted 18yrs posted by denkedranjoe