Field-Programmable Gate Arrays

FPGA reprogrammable? (urgent)

hello.... i wanted to know if fpgas were reprogrammable... if i have a virtex2pro board, use it for a system, and later...

3 comments posted 18yrs

posted by vikram788

3 comments posted 18yrs posted by vikram788

Deskew Clock on Synchronous Bus

I am having difficulties in trying to deskew the Clock on a synchronous local bus interface between a Virtex4 FPGA and...

4 comments posted 18yrs

posted by bill.ngo

4 comments posted 18yrs posted by bill.ngo

ANNOUNCE: TimingAnalyzer -- new updated version

Hello All, A new version beta 0.83 is now available. The following changes and additions have occurred. * Improved Imag...

3 comments posted 18yrs

posted by timinganalyzer

3 comments posted 18yrs posted by timinganalyzer

Nastat vs.kitkat tuore tutkimus

Transmutaatiotekniikasta. *Maassamme ydinalalla on tuskin mitään niin tarkoin TABU:na pirettyä systeemiä, kuin mahdolli...

0 comments posted 18yrs

posted by artturi

0 comments posted 18yrs posted by artturi

Aldec Active-HDL and Xilinx/Altera FPGA-vendor library support

I've noticed Modelsim directly compiles the vendor's simulation-libraries from the HDL-source (either VHDL or Verilog.)...

4 comments posted 18yrs

posted by noone

4 comments posted 18yrs posted by noone

Nutritional yeast

Yksinkertainen kysymys: "Mitä Suomen valtion kansantalous saa tehtyä niillä 100% puhtailla energiamäärillään, joita sil...

0 comments posted 18yrs

posted by severi

0 comments posted 18yrs posted by severi

NIOS-II+LAN91C111

Hi,everyone,I am now doing a work about ALTERA nios-II.The FPGA I use is cycII-60,and the cpu is NIOS-II f,sdram ,lan91...

3 comments posted 18yrs

posted by bjzhangwn

3 comments posted 18yrs posted by bjzhangwn

Extracting market feedback from Usenet traffic

I have monitored this group for a while and written a thesis about the possibility to extract market feedback from Usen...

0 comments posted 18yrs

posted by fbertram

0 comments posted 18yrs posted by fbertram

Re: 1 Pin MTE Cable

"HT-Lab" schrieb im Newsbeitrag news:DTd2k.59$ snipped-for-privacy@newsfe05.ams... > Hi all, > > Does anybody know a go...

0 comments posted 18yrs

posted by techseller

0 comments posted 18yrs posted by techseller

FPGA to FLASH and back?

Hi, I'd like to use an Intel StrataFlash Memory 28F320J3A with my Virtex4 FPGA and write / read data from it. Is there...

3 comments posted 18yrs

posted by denkedranjoe

3 comments posted 18yrs posted by denkedranjoe

length compensation for RocketIO channels

Hi there, I'm designing a PCB that incorporates a Virtex4 FX60 with 16 RocketIOs. All RocketIOs function only as a rece...

1 comments posted 18yrs

posted by denkedranjoe

1 comments posted 18yrs posted by denkedranjoe

ANNOUNCE: SiliconBlue Pioneers New FPGA Technology for Handheld, Ultra-Low Power Applications

SiliconBlue Pioneers New FPGA Technology for Handheld, Ultra-Low Power Applications Monday, SiliconBlue(tm) announced a...

2 comments posted 18yrs

posted by sales_-AT-_siliconbluetech.com

2 comments posted 18yrs posted by sales_-AT-_siliconbluetech.com

Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams

> [...] > For all the talk of enhancing the user's experience it seems obvious > to me that MS don't give a s*it about...

15 comments posted 18yrs

posted by yates

15 comments posted 18yrs posted by yates

HDL tricks for better timing closure in FPGAs

Hi, I am working with FPGAs and trying to take advantage of the parallelism that is available in them. My design is in...

13 comments posted 18yrs

posted by jaydev.shelat

13 comments posted 18yrs posted by jaydev.shelat

Your favourite DSP textbooks/websites?

hi folks You may have noticed that I've been struggling to explain some rather basic stuff about FIR filters to someone...

7 comments posted 18yrs

posted by jonathan.bromley

7 comments posted 18yrs posted by jonathan.bromley