Hi all
I have questions about bitstream relocation in VirtexII FPGAs. We have already developed software based on the old Jbits package from Xilinx for doing small bits manipualations bitstream relacation for Virtex devices, but we are facing difficulties in finding documentation about how to perform significant-size IP-core bitstreams (50,000 gates or more) relocation in VirtexII devices. Can you give some hint on where such documentation can be found, if it exists?
We are implementing a configurations controller manager in hardware, to allow automated swap of IPs in a number of identical size reconfigurable areas defined using the Modular Design flow (even though the current documentation suggests that it is complicated to make things work with more than one reconfigurable area at the same time, we have managed to define and "almost" use 2 such areas). The idea is: given a temporal schedule for reconfigurable IPs and apply this using the ICAP interface to partially reconfigure the device in one of the areas. Having more than one area is fundamental to allow bitstream prefetch for hiding reconfiguration latency.
Thanks in advance for any help.
Ewerson L. S. Carvalho, Master Student - Informatics Institute, PUCRS Mail Address: Av Ipiranga, 6681, Prédio 16. Porto Alegre, RS, Brazil CEP:90619-900 - Phone:+55 51 3320 3611 - Fax:+55 51 3320 3758 e-mail: snipped-for-privacy@inf.pucrs.br - URL: