> > My approach would be to generate a synchronous CE (clock disable) signal
> > and distribute it. Now I have a synchronous signal distribution problem
> > that I can analyze the conventional way. If the prop delay is less than
> > a clock period, there is no problem. Otherwise I can resort to
> pipelining...
> > That means, you are in charge and not at the mercy of some loosely
> > specified asynchronous delay
>
> Peter, do you recommend using these synchronised resets with the asynch
> reset
> input of your flip-flops, or do they then become part of the
> synchronous inputs?
>
> Nial.
> ------------------------------------------------
> Nial Stewart Developments Ltd
> FPGA and High Speed Digital Design
>formatting link