Field-Programmable Gate Arrays

basic chipscope pro query

Hello, I am new to chipscope pro.i read lot of documents but unable to get exact information.i worked with counter exam...

4 comments posted 18yrs

posted by irfan.mohammed

4 comments posted 18yrs posted by irfan.mohammed

ISE Simulator

Xilinx ISE 9.2 and 10.1 (Webpack) signal cntr: integer range 0 to 3; ... if(clk'event and clk='1') then cntr

4 comments posted 18yrs

posted by meralonurlu

4 comments posted 18yrs posted by meralonurlu

synthesis warning

Hi, during synthesis I get many warnings. One of them is : WARNING:Xst:2404 - FFs/Latches (without init value) have a c...

2 comments posted 18yrs

posted by webmaster

2 comments posted 18yrs posted by webmaster

Xilinx ISE speed files compatibility

Does anyone know if I can copy a speed file from ISE10.1 to ISE8.2? They are of very much different size, which seems t...

4 comments posted 18yrs

posted by mbmsv

4 comments posted 18yrs posted by mbmsv

Xilinx 10.1 service-pack error: ./setup: line 41: 1472 Segmentation fault

On my Centos 5.2 (x86 32-bit) Linux box, I've noticed a problem with the 10.1 service-packs. If I unzip to a directory...

0 comments posted 18yrs

posted by root

0 comments posted 18yrs posted by root

HELP! How do I install Xilinx ISE WebPack?

I'm using Damn Small Linux version 3.4.8. I downloaded the file 10.1_Webinstall.zip to my hard drive. When I open this...

1 comments posted 18yrs

posted by jason_hsu

1 comments posted 18yrs posted by jason_hsu

Serial Pheripheral Interface for XILINX FPGA

Hi, I have one question if anyone can give me some clues. I need to realize SPI (Serial Pheriferal Interface for my pro...

5 comments posted 18yrs

posted by Zorjak

5 comments posted 18yrs posted by Zorjak

Single ended interface at 70Mhz for FPGAs

hi, I am looking for connecting my proprietary 8 bit bus interface across two Xilinx FPGAs across the back plane, (10 i...

6 comments posted 18yrs

posted by togoli

6 comments posted 18yrs posted by togoli

Free Webinars on PMP Certification Awareness and Roadmap

Dear Freinds I came across a website which conducts Free Webinars on PMP Certification (Project Management Institute, U...

0 comments posted 18yrs

posted by makarand794

0 comments posted 18yrs posted by makarand794

FiFo Help Needed

Can anyone help me check my codes? I implemented it, but when I run on Modelsim, there doesnt seem to be any data comin...

9 comments posted 18yrs

posted by me75

9 comments posted 18yrs posted by me75

Effect of reheating and reballing on reliability of Xilinx chips

Hi Ausitn & Peter and whoever else from Xilinx is listening, I need your opinion on how number of reheating cycles with...

0 comments posted 18yrs

posted by mbmsv

0 comments posted 18yrs posted by mbmsv

Xilinx XPS and Multiple Microblaze

Hi, I know that it is possible to put multiple microblaze in a virtexIIPro. I am trying to design one architecture with...

2 comments posted 18yrs

posted by pbantunez

2 comments posted 18yrs posted by pbantunez

External Clock Generator

Hi I wanna use an external function generator to feed the FPGA with the clock signal. I have come across a function gen...

3 comments posted 18yrs

posted by Rob_Berger

3 comments posted 18yrs posted by Rob_Berger

Constraints for router

Hi, I need to ensure that two FFs are placed close to each other. Does anybody know if it's possible? Can I use any cons...

1 comments posted 18yrs

posted by tiago.bn

1 comments posted 18yrs posted by tiago.bn

OPB_CENTRAL_DMA

Has anybody used central_dma to copy data between peripherals and processors, or between two buffers in bram mermory. I...

5 comments posted 18yrs

posted by pbantunez

5 comments posted 18yrs posted by pbantunez