Field-Programmable Gate Arrays

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Help to SImulate Uart TX

I'm using the following code. I've managed to make it work on my fpga before. but when I try to simulate on my modelsim...
7 comments posted 18yrs
posted by me75
7 comments posted 18yrs posted by me75

QPSK SymbolRate generator ...

I have built a QPSK modulator, but I have some doubts about the generation of SymbolRate variable. The SymbolRate range...
7 comments posted 18yrs
posted by 78kappa78(at)virgilio(dot)it
7 comments posted 18yrs posted by 78kappa78(at)virgilio(dot)it

basic chipscope pro query

Hello, I am new to chipscope pro.i read lot of documents but unable to get exact information.i worked with counter exam...
4 comments posted 18yrs
posted by irfan.mohammed
4 comments posted 18yrs posted by irfan.mohammed

ISE Simulator

Xilinx ISE 9.2 and 10.1 (Webpack) signal cntr: integer range 0 to 3; ... if(clk'event and clk='1') then cntr
4 comments posted 18yrs
posted by meralonurlu
4 comments posted 18yrs posted by meralonurlu

synthesis warning

Hi, during synthesis I get many warnings. One of them is : WARNING:Xst:2404 - FFs/Latches (without init value) have a c...
2 comments posted 18yrs
posted by webmaster
2 comments posted 18yrs posted by webmaster

Xilinx ISE speed files compatibility

Does anyone know if I can copy a speed file from ISE10.1 to ISE8.2? They are of very much different size, which seems t...
4 comments posted 18yrs
posted by mbmsv
4 comments posted 18yrs posted by mbmsv

HELP! How do I install Xilinx ISE WebPack?

I'm using Damn Small Linux version 3.4.8. I downloaded the file 10.1_Webinstall.zip to my hard drive. When I open this...
1 comments posted 18yrs
posted by jason_hsu
1 comments posted 18yrs posted by jason_hsu

Serial Pheripheral Interface for XILINX FPGA

Hi, I have one question if anyone can give me some clues. I need to realize SPI (Serial Pheriferal Interface for my pro...
5 comments posted 18yrs
posted by Zorjak
5 comments posted 18yrs posted by Zorjak

Single ended interface at 70Mhz for FPGAs

hi, I am looking for connecting my proprietary 8 bit bus interface across two Xilinx FPGAs across the back plane, (10 i...
6 comments posted 18yrs
posted by togoli
6 comments posted 18yrs posted by togoli

FiFo Help Needed

Can anyone help me check my codes? I implemented it, but when I run on Modelsim, there doesnt seem to be any data comin...
9 comments posted 18yrs
posted by me75
9 comments posted 18yrs posted by me75

Xilinx XPS and Multiple Microblaze

Hi, I know that it is possible to put multiple microblaze in a virtexIIPro. I am trying to design one architecture with...
2 comments posted 18yrs
posted by pbantunez
2 comments posted 18yrs posted by pbantunez

External Clock Generator

Hi I wanna use an external function generator to feed the FPGA with the clock signal. I have come across a function gen...
3 comments posted 18yrs
posted by Rob_Berger
3 comments posted 18yrs posted by Rob_Berger